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UCC2626DW Datasheet(PDF) 7 Page - Texas Instruments |
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UCC2626DW Datasheet(HTML) 7 Page - Texas Instruments |
7 / 23 page UCC2626, UCC3626 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 7 www.ti.com pin descriptions SYNCH: The SYNCH input is used to synchronize the PWM oscillator with an external digital clock. When using the SYNCH feature, a resistor equal to R_TACH must be placed in parallel with CT. When not using the SYNCH feature, SYNCH must be grounded. SNS_NI, SNS_I: These inputs are the noninverting and inverting inputs to the current sense amplifier, respectively. The integrated amplifier is configured for a gain of five. An absolute value function is also incorporated into the output in order to provide a representation of actual motor current when operating in four-quadrant mode. TACH_OUT: TACH_OUT is the output of a monostable triggered by a change in the commutation state, thus providing a variable duty cycle, frequency output. The on time of the monostable is set by the timing capacitor connected to C_TACH. The monostable is capable of being retriggered if a commutation occurs during its on-time. R_TACH: A resistor connected between R_TACH and ground programs the current for both the oscillator and tachometer. VDD: VDD is the input supply connection for this device. Undervoltage lockout keeps the outputs off for inputs below 10.5 V. The input should be bypassed with a 0.1- µF ceramic capacitor, minimum. VREF: VREF is a 5-V, 2% trimmed reference output with 5 mA of maximum available output current. This pin should be bypassed to ground with a ceramic capacitor with a value of at least 0.1 µF. APPLICATION INFORMATION Table 1 provides the decode logic for the six outputs, AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and HALLC inputs. Table 1. Commutation Truth Table BRAKE COAST DIR_IN HALL INPUTS HIGH-SIDE OUTPUTS LOW-SIDE OUTPUTS BRAKE COAST DIR_IN A B C A B C A B C 0 0 1 1 0 1 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 X 1 X X X X 0 0 0 0 0 0 1 0 X X X X 0 0 0 1 1 1 0 0 X 1 1 1 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 0 0 |
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