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UCC2583DTR Datasheet(PDF) 4 Page - Texas Instruments |
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UCC2583DTR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 18 page  4 UCC1583 UCC2583 UCC3583 Power Stage Circuit Configuration The UCC3583 is designed for use in a post regulator ap- plication for tightly regulating auxiliary outputs in a multi- ple output converter. The post regulation is applied to the secondary side power pulse of a power transformer where the power pulse is controlled by the feedback sig- nal from the main output. In order to simplify the applica- tion of the UCC3583, it is required that the IC be referenced to the positive output terminal and the output filter inductor be placed in the return path. The placement of the inductor in the return path facilitates better EMI performance, in addition to making magnetic designs and terminations easier to implement. Typical set-up and circuit waveforms of the UCC3583 system application are shown in Figure 1. Figure 2 shows waveforms for a single ended output rectifier application of the UCC3583 shown on page 1. The UCC3583 can also be used in half bridge rectifier applications as shown by the circuit and waveforms depicted in Figures 3 and 4. Referencing the IC to the positive output terminal creates a require- ment for a floating bias voltage for the IC which can be referenced to the same positive voltage terminal. Possi- ble implementations of deriving the floating bias voltage are shown in Figure 5. APPLICATION INFORMATION CAO: Output of the current error amplifier. Averaging of the sensed current signal is provided by connecting an integrating capacitor between ILIM and CAO. CAO feeds into the PWM comparator input and controls the loop when its voltage is higher than the voltage at COMP (output of the voltage error amplifier). COM: Signal ground for the chip. It is connected to the positive terminal of the output voltage being regulated by the IC. COMP: Output of the voltage error amplifier fed into the PWM comparator. Loop compensation components are connected between COMP and INV. CS: Non-inverting input of the current error amplifier. The sensed current signal from the current sense resistor is connected to this pin. By making the signal at CS proportional to the output voltage, effective current foldback limiting can be provided. GATE: Gate drive output for the power switch FET. The drive pin has a 0.5A sink/1.5A source capability and very low output off-state impedance. ILIM: Inverting input of the current error amplifier. It sets the DC limit for the output current. INV: Inverting input of the voltage error amplifier. The feedback signal is connected to this pin using a resistive divider between REF and –VO. PCOM: Power ground for the chip. It is connected to the source terminal of the MOSFET being regulated by the IC. RAMP: This pin is the input to the PWM comparator and provides a ramp signal for generation of the PWM signal. A capacitor to COM and a resistor to REF set the charging rate for the ramp. An internal current source of 1mA discharges RAMP when synchronization signal appears or when RAMP crosses a 4V threshold. In the intended mode of operation, the switching frequency is determined by the secondary power pulse. The RC components at RAMP should be selected to give an appropriately sized ramp signal. In the absence of a synchronizing pulse, these RC components determine the free running frequency of the controller. REF: Precision 5V reference pin. REF stays off until VDD exceeds 9V and turns off again when VDD drops below 8.4V. Bypass REF to COM. SS: This pin provides a soft start function. A capacitor to REF programs the soft start time. During soft start, the PWM comparator is controlled by the soft start voltage resulting in a slow increase in output duty cycle. Once the soft start capacitor is discharged, output control is dictated by the larger of the output at CAO or COMP. SYNC: Synchronization input pin. It is connected to a signal representative of the secondary power pulse. One possible implementation is to use a resistive divider between terminal S2 of the secondary winding shown in Figure 1 and REF for generating the input to the SYNC pin. The synchronizing comparator is referenced to 0.5V and has ±500mV of hysteresis. The trip levels are approximate 1.0V and 0.0V. The designer should prevent the SYNC pin from exceeding 0.3V below ground as this will turn on the ESD diode. VD: Power supply for the output driver. VD should be tied to VDD in the application. VDD: Power supply for the chip. VDD should be bypassed to COM. VDD has to be 9V for the IC to start and 8.4V for it to remain operational. A shunt clamp from VDD to COM limits the supply voltage to 14V. PIN DESCRIPTIONS |
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Similar Description - UCC2583DTR |
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