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UCC2894PWG4 Datasheet(PDF) 7 Page - Texas Instruments |
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UCC2894PWG4 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 41 page  UCC2891, UCC2892 UCC2893, UCC2894 SLUS542F − OCTOBER 2003 − REVISED JULY 2009 7 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME UCC2891 UCC2893 UCC2892 UCC2894 I/O DESCRIPTION AUX 12 12 O This output drives the auxiliary clamp MOSFET which is turned on when the main PWM switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A source turn-on current and 2-A sink turn-off current. CS 7 7 I This pin is used to sense the peak current utilized for current mode control and for current limiting functions. The peak signal which can be applied to this pin before pulse-by-pulse current limiting activates is approximately 0.75 V for the UCC2891 and UCC2893 and 1.27 V for the UCC2892 and UCC2894. FB 9 9 I This pin is used to bring the error signal from an external optocoupler or error amplifier into the PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoup- ler is used to pull the control pin closer to GND to reduce the pulse width of the OUT output driving the main power switch of the converter. GND 6 6 − This pin serves as the fundamental analog ground for the PWM control circuitry. This pin should be connected to PGND directly at the device. LINEOV − 16 I For the UCC2892/4, provides the LINE overvoltage function. LINEUV 15 15 I This pin provides a means to accurately enable/disable the power converter stage by moni- toring the bulk input voltage or another parameter. When the circuit initially starts (or restarts from a disabled condition), a rising input on LINEUV enables the outputs when the threshold of 1.27 V is crossed. After the circuit is enabled, then a falling LINEUV signal disables the outputs when the same threshold is reached. The hysteresis between the two levels is pro- grammed using an internal current source. OUT 13 13 O This output pin drives the main PWM switching element MOSFET in an active clamp control- ler. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sink turn-off current. A 10−k Ω resistor is recommended to connect this pin to PGND. PGND 11 11 − The PGND should serve as the current return for the high-current output drivers OUT and AUX. Ideally, the current path from the outputs to the switching devices, and back would be as short as possible, and enclose a minimal loop area. RSLOPE 8 8 I A resistor connected from this pin to GND programs an internal current source that sets the slope compensation ramp for the current mode control circuitry. RTDEL 1 1 I A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs to accommodate the resonant transitions of the active clamp power converter. RTOFF 3 3 I A resistor connected from this pin to GND programs an internal current source that dis- charges the internal timing capacitor. RTON 2 2 I A resistor connected from this pin to GND programs an internal current source that charges the internal timing capacitor. SS/SD 10 10 I A capacitor from SS/SD to ground is charged by an internal current source of IRTON to pro- gram the soft-start interval for the controller. During a fault condition this capacitor is dis- charged by a current source equal to IRTON. SYNC 5 5 I The SYNC pin serves as a unidirectional synchronization input for the internal oscillator. The synchronization function is implemented such that the user programmable maximum duty cycle (set by RTON and RTOFF) remains accurate during synchronized operation. VDD 14 14 I This is the power supply for the device. There should be a 1- µF capacitor directly from VDD to PGND. The capacitor value should be minimum 10 times greater than that on VREF. PGND and GND should be connected externally and directly from PGND to GND. VIN 16 − I For the UCC2891 and UCC2893, this pin is connected to the input power rail directly. Inside the device, a high-voltage start-up device is utilized to provide the start-up current for the controller until a bootstrap type bias rail becomes available. VREF 4 4 O This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA. Since this reference provides the supply rail for internal logic, it should be bypassed to AGND as close as possible to the device. The VREF bias profile may not be monotonic before VDD reached 5 V. |
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