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DD8C32_64x64A.fm - Rev. J 8/08 EN

4

©2003 Micron Technology, Inc. All rights reserved.

256MB, 512MB (x64, SR) 184-Pin DDR SDRAM UDIMM

Pin Assignments and Descriptions

Table 6:

Pin Descriptions

Symbol

Type

Description

A0–A12

Input

(SSTL_18)

Address inputs: Provide the row address for ACTIVE commands, and the

column address and auto precharge bit (A10) for READ/WRITE commands, to

select one location out of the memory array in the respective device bank. A10

sampled during a PRECHARGE command determines whether the PRECHARGE

applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all

device banks (A10 HIGH). The address inputs also provide the op-code during

a MODE REGISTER SET command. BA0, BA1 define which mode register (mode

register or extended mode register) is loaded during the LOAD MODE

REGISTER command.

BA0, BA1

Input

(SSTL_18)

Bank address: BA0, BA1 define to which device bank an ACTIVE, READ,

WRITE, or PRECHARGE command is being applied.

CK0, CK0#,

CK1, CK1#,

CK2, CK2#

Input

(SSTL_18)

Clock: CK and CK# are differential clock inputs. All address and control input

signals are sampled on the crossing of the positive edge of CK and the

negative edge of CK#. Output data (DQ and DQS) is referenced to the

crossings of CK and CK#.

CKE0

Input

(SSTL_18)

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)

deactivates the internal clock, input buffers, and output drivers.

DM0–DM7

Input

(SSTL_18)

Input data mask: DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH, along with that input data, during a write

access. DM is sampled on both edges of DQS. Although DM pins are input-

only, the DM loading is designed to match that of DQ and DQS pins.

RAS#, CAS#, WE#

Input

(SSTL_18)

Command inputs: RAS#, CAS#, and WE# (along with S#) define the

command being entered.

S0#

Input

(SSTL_18)

Chip selects: S# enables (registered LOW) and disables (registered HIGH) the

command decoder.

SA0–SA2

Input

(SSTL_18)

Presence-detect address inputs: These pins are used to configure the

presence-detect device.

SCL

Input

(SSTL_18)

Serial clock for presence-detect: SCL is used to synchronize the presence-

detect data transfer to and from the module.

DQ0–DQ63

I/O

(SSTL_18)

Data input/output: Data bus.

DQS0–DQS7

I/O

(SSTL_18)

Data strobe: Output with read data, input with write data. DQS is edge-

aligned with read data, center-aligned with write data. Used to capture data.

SDA

I/O

(SSTL_18)

Serial presence-detect data: SDA is a bidirectional pin used to transfer

addresses and data into and out of the presence-detect portion of the

module.

Supply

Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V)

Supply

Serial EEPROM positive power supply: +2.3V to +3.6V.

Supply

Supply

Ground.

DNU

–

Do not use: These pins are not connected on these modules, but are assigned

on other modules in this product family.

NC

–

No connect: These pins are not connected on the module.