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M393B1K70CH0 Datasheet(PDF) 3 Page - Samsung semiconductor |
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M393B1K70CH0 Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 53 page - 3 - datasheet DDR3 SDRAM Rev. 1.0 Registered DIMM Table Of Contents 240pin Registered DIMM based on 2Gb C-die 1. DDR3 Registered DIMM Ordering Information ............................................................................................................. 5 2. Key Features................................................................................................................................................................. 5 3. Address Configuration .................................................................................................................................................. 5 4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ 6 5. Pin Description ............................................................................................................................................................. 7 6. ON DIMM Thermal Sensor ........................................................................................................................................... 7 7. Input/Output Functional Description.............................................................................................................................. 8 8. Pinout Comparison Based On Module Type................................................................................................................. 9 9. Registering Clock Driver Specification.......................................................................................................................... 10 9.1 Timing & Capacitance values .................................................................................................................................. 10 9.2 Clock driver Characteristics..................................................................................................................................... 10 10. Function Block Diagram:............................................................................................................................................. 11 10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11 10.2 4GB,512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) .................................................................. 12 10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13 10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ..................................................................... 14 10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) .................................................................... 16 10.6 16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) ................................................................... 17 11. Absolute Maximum Ratings ........................................................................................................................................ 22 11.1 Absolute Maximum DC Ratings............................................................................................................................. 22 11.2 DRAM Component Operating Temperature Range .............................................................................................. 22 12. AC & DC Operating Conditions................................................................................................................................... 22 12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 22 13. AC & DC Input Measurement Levels .......................................................................................................................... 23 13.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 23 13.2 VREF Tolerances. ................................................................................................................................................. 24 13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 25 13.3.1. Differential Signals Definition ......................................................................................................................... 25 13.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 25 13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 26 13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 27 13.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 27 13.5 Slew rate definition for Differential Input Signals ................................................................................................... 27 14. AC & DC Output Measurement Levels ....................................................................................................................... 28 14.1 Single Ended AC and DC Output Levels............................................................................................................... 28 14.2 Differential AC and DC Output Levels ................................................................................................................... 28 14.3 Single-ended Output Slew Rate ............................................................................................................................ 28 14.4 Differential Output Slew Rate ................................................................................................................................ 29 15. DIMM IDD specification definition ............................................................................................................................... 30 16. IDD SPEC Table ......................................................................................................................................................... 32 17. Input/Output Capacitance ........................................................................................................................................... 35 18. Electrical Characteristics and AC timing ..................................................................................................................... 37 18.1 Refresh Parameters by Device Density................................................................................................................. 37 18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 37 18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 37 18.3.1. Speed Bin Table Notes .................................................................................................................................. 40 19. Timing Parameters by Speed Grade .......................................................................................................................... 41 19.1 Jitter Notes ............................................................................................................................................................ 44 19.2 Timing Parameter Notes........................................................................................................................................ 45 20. Physical Dimensions................................................................................................................................................... 46 20.1 256Mbx8 based 256Mx72 Module (1 Rank) - M393B5773CH0............................................................................ 46 20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs46 |
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