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PGA5807 Datasheet(PDF) 5 Page - Texas Instruments |
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PGA5807 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 27 page  PGA5807 www.ti.com SBAS617B – MAY 2013 – REVISED JUNE 2013 Table 1. PIN FUNCTIONS NAME NO. FUNCTION DESCRIPTION AVDD 17, 28, 31, 49, 62-64 Supply Analog supply pin, 3.3 V AVSS 19, 20, 24, 27, 29, 50, 54, 61 Ground Analog ground When RESET is high, this pin is used to program the PGA gain. GAIN0 51 Digital input Refer to Table 2 for more details. Note: Use 3.3-V logic. When RESET is high, this pin is used to program the PGA gain. GAIN1 52 Digital input Refer to Table 2 for more details. Note: Use 3.3-V logic. When RESET is high, this pin is used to program the PGA gain. GAIN2 56 Digital input Refer to Table 2 for more details. Note: Use 3.3-V logic. INM1 to Complimentary analog inputs for channels 1 to 8. 2, 4, 6, 8, 10, 12, 14, 16 Input INM8 The dc input common-mode can be 2.1 V ± 200 mV. Analog inputs for channels 1 to 8. INP1 to INP8 1, 3, 5, 7, 9, 11, 13, 15 Input The dc input common-mode can be 2.1 V ± 200 mV. NC 21-23, 25, 26, 30, 32 — Unused pins; do not connect OUTM1 to 33, 35, 37, 39, 41, 43, 45, 47 Output Complimentary output pins with a 0.95-V common-mode voltage OUTM8 OUTP1 to 34, 36, 38, 40, 42, 44, 46, 48 Output Output pins with a 0.95-V common-mode voltage OUTP8 Partial power-down control pin for the entire device with an internal 20-k Ω PDN 53 Digital input pull-down resistor; active high. Note: Use 3.3-V logic. RESET 60 Digital input Logic hardware reset pin. Note: Use 3.3-V logic. Serial interface clock pin with an internal 20-k Ω pull-down resistor. Note: Use SCLK 59 Digital input 3.3-V logic. Serial interface data input with an internal 20-k Ω pull-down resistor. When RESET is high, the corner frequency for the antialias filter can be SDATA 58 Digital input programmed to a lower frequency (60 MHz) by setting this pin high. Note: Use 3.3-V logic. SDOUT 55 Digital output Serial interface readout pin Serial interface enabled for channels 1 to 8 with an internal 20-k Ω pull-up SEN 57 Digital input resistor; active low. Note: Use 3.3-V logic. VBIAS 18 Decap Bias voltage; bypass to ground with a 1- μF capacitor or greater Table 2. PGA Gain Control GAIN[2:0] PGA_GAIN (dB) 000 18 001 15 010 12 011 9 100 6 101 3 110 0 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: PGA5807 |
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