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MT41J128M16HA-125 Datasheet(PDF) 8 Page - Micron Technology |
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MT41J128M16HA-125 Datasheet(HTML) 8 Page - Micron Technology |
8 / 206 page Figure 103: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 190 Figure 104: Dynamic ODT: Without WRITE Command .................................................................................. 190 Figure 105: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 191 Figure 106: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 192 Figure 107: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 192 Figure 108: Synchronous ODT ...................................................................................................................... 194 Figure 109: Synchronous ODT (BC4) ............................................................................................................. 195 Figure 110: ODT During READs .................................................................................................................... 197 Figure 111: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 199 Figure 112: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off ) Entry ............ 201 Figure 113: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off ) Exit ............... 203 Figure 114: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 205 Figure 115: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 205 2Gb: x4, x8, x16 DDR3 SDRAM Features PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. |
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