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TLV70025DCKR Datasheet(PDF) 10 Page - Texas Instruments |
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TLV70025DCKR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 35 page  TLV700xx SLVSA00D – SEPTEMBER 2009 – REVISED NOVEMBER 2012 www.ti.com APPLICATION INFORMATION The TLV700xx belongs to a new family of next- generation value LDO regulators. These devices Board Layout Recommendations to Improve consume low quiescent current and deliver excellent PSRR and Noise Performance line and load transient performance. These Input and output capacitors should be placed as characteristics, combined with low noise, very good close to the device pins as possible. To improve ac PSRR with little (VIN – VOUT) headroom, make this performance such as PSRR, output noise, and family of devices ideal for RF portable applications. transient response, it is recommended that the board This family of regulators offers current limit and be designed with separate ground planes for VIN and thermal protection, and is specified from –40°C to VOUT, with the ground plane connected only at the +125°C. GND pin of the device. In addition, the ground connection for the output capacitor should be Input and Output Capacitor Requirements connected directly to the GND pin of the device. High 1.0- μF X5R- and X7R-type ceramic capacitors are ESR capacitors may degrade PSRR performance. recommended because these capacitors have minimal variation in value and equivalent series Internal Current Limit resistance (ESR) over temperature. The TLV700xx internal current limit helps to protect However, the TLV700xx is designed to be stable with the regulator during fault conditions. During current an effective capacitance of 0.1 μF or larger at the limit, the output sources a fixed amount of current output. Thus, the device is stable with capacitors of that is largely independent of the output voltage. In other dielectric types as well, as long as the effective such a case, the output voltage is not regulated, and capacitance under operating bias voltage and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor temperature is greater than 0.1 μF. This effective dissipates (VIN – VOUT) × ILIMIT until thermal shutdown capacitance refers to the capacitance that the LDO is triggered and the device turns off. As the device sees under operating bias voltage and temperature cools down, it is turned on by the internal thermal conditions; that is, the capacitance after taking both shutdown circuit. If the fault condition continues, the bias voltage and temperature derating into device cycles between current limit and thermal consideration. In addition to allowing the use of shutdown. See the Thermal Information section for cheaper dielectrics, this capability of being stable with more details. 0.1- μF effective capacitance also enables the use of The PMOS pass element in the TLV700xx has a smaller footprint capacitors that have higher derating built-in body diode that conducts current when the in size- and space-constrained applications. voltage at OUT exceeds the voltage at IN. This Note that using a 0.1- μF rated capacitor at the output current is not limited, so if extended reverse voltage of the LDO does not ensure stability because the operation is anticipated, external limiting to 5% of the effective capacitance under the specified operating rated output current is recommended. conditions would be less than 0.1 μF. Maximum ESR should be less than 200 m Ω. Shutdown Although an input capacitor is not required for The enable pin (EN) is active high. The device is stability, it is good analog design practice to connect enabled when voltage at EN pin goes above 0.9V. a 0.1- μF to 1.0-μF, low ESR capacitor across the IN This relatively lower value of voltage required to turn pin and GND in of the regulator. This capacitor the LDO on can be exploited to power the LDO with a counteracts reactive input sources and improves GPIO of recent processors whose GPIO Logic 1 transient response, noise rejection, and ripple voltage level is lower than traditional microcontrollers. rejection. A higher-value capacitor may be necessary The device is turned OFF when the EN pin is held at if large, fast rise-time load transients are anticipated, less than 0.4V. When shutdown capability is not or if the device is not located close to the power required, EN can be connected to the IN pin. source. If source impedance is more than 2 Ω, a 0.1- μF input capacitor may be necessary to ensure stability. 10 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated |
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