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QG80333M500 Datasheet(PDF) 9 Page - Intel Corporation |
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QG80333M500 Datasheet(HTML) 9 Page - Intel Corporation |
9 / 48 page Specification Update 9 Intel® 80333 I/O Processor Summary Table of Changes 31 XX 24 No Fix Tc1(min) of the PCI-X clock observed to be marginally less than the requirement specified for the PCI-X (Mode 1, class1) clock jitter. 32 XX 25 No Fix I2C Control Register reset bit does not function 33 XX 25 No Fix MSI Hot-Plug Interrupt issue 34 XX 25 No Fix Under certain conditions, inbound prefetched PCI read requests may return wrong data to the requestor 35 X 26 Fixed Internal Clock Misalignment Can Cause Processor Hang. 36 XX 26 No Fix Spurious DMA0 End-Of-Transfer Interrupt Core Errata No. Steppings Page Status Errata A-0 A-1 1 XX 27 No Fix Abort is missed when lock command is outstanding 2 XX 27 No Fix Aborted store that hits the data cache can mark write-back data as dirty 3 XX 28 No Fix Performance Monitor Unit event 0x1 can be incremented erroneously by unrelated events 4 XX 28 No Fix In Special Debug State, back-to-back memory operations—in which the first instruction aborts—can cause a hang 5 XX 29 No Fix Accesses to the CP15 ID Register with opcode2 > 001b returns unpredictable values 6 XX 29 No Fix Disabling and re-enabling the MMU can hang the core or cause it to execute the wrong code 7 XX 30 No Fix Updating the JTAG parallel registers requires an extra TCK rising edge 8 XX 30 No Fix Non-branch instruction in vector table might execute twice after a thumb mode exception Non-Core Errata (Sheet 2 of 2) No. Stepping Page Status Errata A-0 A-1 Specification Changes No. Steppings Page Status Specification Changes A-0 A-1 1 XX 31 Doc Recommended DLL register values 2 XX 31 Doc DDR-II JEDEC initialization sequence includes writes to EMRS2 and EMRS3 3 XX 32 Doc REFCLK relationship to voltage rails 4 XX 32 Doc Case temperature (Tcase) change 5 XX 32 Doc PWRGD and RSTIN# sequencing 6 X 32 Fixed Internal Clock Misalignment. |
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