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NQ80333M667 Datasheet(PDF) 8 Page - Intel Corporation |
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NQ80333M667 Datasheet(HTML) 8 Page - Intel Corporation |
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8 / 48 page  8 Specification Update Intel® 80333 I/O Processor Summary Table of Changes Non-Core Errata (Sheet 1 of 2) No. Stepping Page Status Errata A-0 A-1 1 XX 14 No Fix CAS latency of three not supported for DDR-II On-Die Termination (ODT) 2 XX 14 No Fix Legacy power fail mechanism does not work 3 XX 14 No Fix A_REQ64# and B_REQ64# initialization pattern timing violation in PCI-33 mode 4 XX 15 No Fix Secondary Bus Number register (PEBSBBNR) provides incorrect bus number 5 XX 15 No Fix Boundary scan multi-chip module implementation 6 XX 15 No Fix PCI Express* traffic class (TC) bit[2] ignored for malformed packet checks 7 XX 16 No Fix Auto-Refresh command also generates a Precharge All command on DDR bus 8 XX 16 No Fix Coalesced writes to 32-bit memory can cause data corruption 9 XX 17 No Fix ATU passing rules operation in PCI mode 10 XX 17 No Fix Secondary bus PCI RST# pulse prior to the rising edge of PWRGD 11 XX 18 No Fix VPD Data Register bit[19] is not read/write 12 XX 18 No Fix PCI Express* Correctable Error Mask Bits 13 XX 18 No Fix DMA CRC result is byte-reversed 14 XX 18 No Fix CRC corruption on PCI-to-local DMA transfers 15 XX 19 No Fix IOAPIC End of Interrupt (EOI) Register is Read-Write, should be Write-Only 16 XX 19 No Fix Unreliable PCI Express* link operation when L0s active state power management is enabled 17 XX 19 No Fix SSE bit set for PERR# assertion when error reporting is masked 18 XX 19 No Fix Data Parity Error detected on PCI/X interface fails to propagate bad parity 19 XX 20 No Fix ATU claims PCI commands 8 and 9 when issued as Dual Address Cycle (DAC) 20 XX 20 No Fix Failure to train down in presence of degraded lane 21 XX 21 No Fix PCI Express* and PCI-X header logs and first-error pointers do not remain sticky through reset 22 XX 21 No Fix Incorrect default value for PCI Express* Flow Control Protocol Error Severity bit 23 XX 21 No Fix Power State bits in PCI Express* Power Management Status and Control Register mistakenly accept reserved values 24 XX 22 No Fix Performance across an upstream ×1 PCI Express* link is less than expected 25 XX 22 No Fix PCI Express* ESD enhancement requires a change to register setting 26 XX 22 No Fix SKP ordered set might not be sent within required interval during link recovery when a packet is pending 27 XX 23 No Fix SERR fatal/non-fatal error message enabled with incorrect error message enabled bit 28 XX 23 No Fix Configuration write to offset 70h of A- and B-bridge (PM_CSR - PCI Express Power Management Control/Status Register) using non-continous byte enables does not capture the data value 29 XX 23 No Fix The 80333 might become unresponsive when transitioning into the D3 power state 30 XX 24 No Fix Bus Interface Unit (BIU) claims DAC addresses in the range of the Memory Mapped Registers (MMR) |
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