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PIC18LF25K50 Datasheet(PDF) 2 Page - Microchip Technology |
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PIC18LF25K50 Datasheet(HTML) 2 Page - Microchip Technology |
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2 / 44 page  PIC18(L)F2X/4XK50 DS41630B-page 2 2012 Microchip Technology Inc. 2.2.1 ICPORT DISABLED Clearing the ICPRT bit in CONFIG4L disables the use of the dedicated port function and leaves the dedicated pins floating. High-voltage and low-voltage programming are performed using the MCLR/VPP, PGC and PGD pins as normal. This is otherwise known as the legacy interface mode, using the standard interface pins. 2.2.2 ICPORT ENABLED Setting the ICPRT bit in CONFIG4L enables the use of the dedicated port function through the dedicated pins. This is the default setting for the ICPRT bit upon start- up or Reset. When using devices in packages other than the 44-pin TQFP, the ICPRT bit must be cleared. The standard interface pins will remain operational, even after the dedicated pins are enabled, unless the user assigns another function to them in firmware. If another function is not assigned to the standard pins and both sets of pins remain operable for program- ming, whichever high-voltage entry pin (the standard VPP pin or the dedicated ICDVPP pin) is activated first will take priority. For high-voltage programming, if high-voltage is detected on the ICDVPP pin first, the standard MCLR/ VPP pin will be ignored and programming must be performed using the ICDPGC and ICDPGD pins. If high-voltage is detected on the MCLR/VPP pin first, the dedicated ICDVPP pin will be ignored and programming must be performed using the PGC and PGD pins. These same rules apply to the low-voltage programming sequence. 2.3 Pin Diagrams The pin diagrams for the PIC18(L)F2X/4XK50 family are shown in Figures 2-1 through 2-4. TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18(L)F2X/4XK50 Pin Name During Programming Pin Pin Type Pin Description MCLR/VPP/RE3 VPP P Programming Enable VDD(1) VDD P Power Supply VSS(1) VSS PGround RB6 PGC I Serial Clock RB7 PGD I/O Serial Data ICDRST/ICDVPP(2) VPP P Programming Enable ICDCLK/ICDPGC PGC I Serial Clock ICDDAT/ICDPGD(2) PGD I/O Serial Data Legend: I = Input, O = Output, P = Power Note 1: All power supply (VDD) and ground (VSS) pins must be connected. 2: Dedicated ICSP/ICD Port available on 44-pin TQFP only when the ICPRT bit in CONFIG4L is enabled. |
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