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PIC18F8720 Datasheet(PDF) 11 Page - Microchip Technology |
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PIC18F8720 Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 380 page  2003-2013 Microchip Technology Inc. DS39609C-page 11 PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description PIC18F6X20 PIC18F8X20 MCLR/VPP MCLR VPP 79 I P ST Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. OSC1/CLKI OSC1 CLKI 39 49 I I CMOS/ST CMOS Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). OSC2/CLKO/RA6 OSC2 CLKO RA6 40 50 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details. |
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