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MAX8973A Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX8973A Datasheet(HTML) 7 Page - Maxim Integrated Products |
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7 / 49 page  MAX8973A 9A, Three-Phase Step-Down Switching Regulator www.maximintegrated.com Maxim Integrated │ 7 Electrical Characteristics (continued) (VIN_ = VCC = VEN = 3.6V, VAGND = VPG_ = VBIASEN = VDVS = 0V, VEN = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Clock Low Period (tLOW) 160 ns Clock High Period (tHIGH) 60 ns Data Setup Time (tSU;DAT) 10 ns Data Hold Time (tHD;DAT) 0 70 ns Minimum SCL Rise Time (tRCL,MIN) 10 ns Maximum SCL Rise Time (tRCL,MAX) 40 ns Minimum Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge Bit (tRCL1,MIN) 10 ns Maximum Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge Bit (tRCL1,MAX) 80 ns Minimum SCL Fall Time (tFCL,MIN) 10 ns Maximum SCL Fall Time (tFCL,MAX) 40 ns Minimum SDA Rise Time (tRDA,MIN) 10 ns Maximum SDA Rise Time (tRDA,MAX) 80 ns Minimum SDA Fall Time (tFDA,MIN) 10 ns Maximum SDA Fall Time (tFDA,MAX) 80 ns Setup Time for STOP Condition (tSU;STO) 160 ns Capacitive Load for Each Bus Line (CB) (Note 3) 100 pF Maximum Pulse Width of Spikes that Must be Suppressed by the Input Filter 10 ns CB = 400pF Clock Frequency (fSCL) (Note 3) 1.7 MHz Setup Time Repeated START Condition (tSU;STA) (Note 3) 160 ns Hold Time Repeated START Condition (tHD;STA) (Note 3) 160 ns Clock Low Period (tLOW) (Note 3) 320 ns |
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