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rfPIC12F675F Datasheet(PDF) 5 Page - Microchip Technology |
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rfPIC12F675F Datasheet(HTML) 5 Page - Microchip Technology |
5 / 136 page 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 5 rfPIC12F675 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The rfPIC12F675 devices have a 13-bit program coun- ter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h - 03FFh) for the rfPIC12F675 devices is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 1K x 14 space. The RESET vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE rfPIC12F675 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose regis- ters and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank. Register locations 20h-5Fh are General Purpose registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS<5>) is the bank select bit. • RP0 = 0 Bank 0 is selected • RP0 = 1 Bank 1 is selected 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the rfPIC12F675 devices. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4). PC<12:0> 13 000h 0004 0005 03FFh 0400h 1FFFh Stack Level 1 Stack Level 8 RESET Vector Interrupt Vector On-chip Program Memory CALL, RETURN RETFIE, RETLW Stack Level 2 Note: The IRP and RP1 bits STATUS<7:6> are reserved and should always be maintained as ‘0’s. |
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