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MCP7940N Datasheet(PDF) 9 Page - Microchip Technology |
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MCP7940N Datasheet(HTML) 9 Page - Microchip Technology |
9 / 42 page 2011-2013 Microchip Technology Inc. DS25010E-page 9 MCP7940N FIGURE 4-2: ACKNOWLEDGE TIMING 4.1.2 DEVICE ADDRESSING AND OPERATION A control byte is the first byte received following the Start condition from the master device (Figure 4-2). The control byte for accessing the SRAM and RTCC registers are set to ‘1101111’. The RTCC registers and the SRAM share the same address space. The last bit of the control byte defines the operation to be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is selected. The next byte received defines the address of the data byte (Figure 4-3). The upper address bits are transferred first, followed by the Least Significant bits (LSb). Following the Start condition, the MCP7940N monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving an ‘1101111’ code, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the MCP7940N will select a read or write operation. FIGURE 4-3: ADDRESS SEQUENCE BIT ASSIGNMENTS SCL 9 8 7 6 5 4 3 2 11 2 3 Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Receiver must release the SDA line at this point so the Transmitter can continue sending data. Data from transmitter Data from transmitter SDA Acknowledge Bit 1 101 R/W X A 0 •• • • •• SRAM RTCC CONTROL BYTE ADDRESS BYTE CONTROL CODE 111 X = Don’t Care |
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