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AD660BN Datasheet(PDF) 10 Page - Analog Devices |
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AD660BN Datasheet(HTML) 10 Page - Analog Devices |
10 / 20 page AD660 Rev. B | Page 10 of 20 THEORY OF OPERATION The AD660 uses an array of bipolar current sources with MOS current steering switches to develop a current proportional to the applied digital word, ranging from 0 mA to 2 mA. A segmented architecture is used, where the most significant four data bits are thermometer decoded to drive 15 equal current sources. The lesser bits are scaled using a R-2R ladder, then applied together with the segmented sources to the summing node of the output amplifier. The internal span/bipolar offset resistor can be connected to the DAC output to provide a 0 V to 10 V span, or it can be connected to the reference input to provide a −10 V to +10 V span. HBE CONTROL LOGIC SER CLR LDAC REF IN 10kΩ 10kΩ 10.05kΩ REF OUT DB0/ DB8/ SIN DB1/DB9/ DATADIR CS DB7/ DB15 AD660 SOUT VOUT AGND SPAN/ BIPOLAR OFFSET DGND –VEE +VCC +VLL 10V REF 16-BIT LATCH 16-BIT DAC 16-BIT LATCH 16 17 18 19 23 24 20 21 22 13 5 1 2 3 4 11 12 14 15 LBE/ CLEAR SELECT Figure 7. Functional Block Diagram ANALOG CIRCUIT CONNECTIONS Internal scaling resistors provided in the AD660 can be connected to produce a unipolar output range of 0 V to 10 V or a bipolar output range of −10 V to +10 V. Gain and offset drift are mini- mized in the AD660 because of the thermal tracking of the scaling resistors with other device components. UNIPOLAR CONFIGURATION The configuration shown in Figure 8 provides a unipolar 0 V to 10 V output range. In this mode, 50 Ω resistors are tied between the SPAN/BIPOLAR OFFSET terminal (Pin 22) and VOUT (Pin 21), and between REF OUT (Pin 24) and REF IN (Pin 23). It is possible to use the AD660 without any external components by tying Pin 24 directly to Pin 23 and Pin 22 directly to Pin 21. Eliminating these resistors increases the gain error by 0.25% of FSR. HBE CONTROL LOGIC SER CLR LDAC REF IN REF OUT AD660 SOUT VOUT AGND OUTPUT R2 50Ω R1 50Ω SPAN/ BIPOLAR OFFSET DGND –VEE +VCC +VLL 10V REF 16-BIT LATCH 16-BIT DAC 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 10kΩ 10kΩ 10.05kΩ DB1/DB9/ DATADIR 11 LBE/ CLEAR SELECT DB0/ DB8/ SIN CS DB7/ DB15 5 12 14 16-BIT LATCH Figure 8. 0 V to 10 V Unipolar Voltage Output If it is desired to adjust the gain and offset errors to zero, this can be accomplished using the circuit shown in Figure 9. The adjustment procedure is as follows: 1. Zero adjust. Turn all bits off and adjust the zero trimmer, R4, until the output reads 0.000000 V (1 LSB = 153 μV). 2. Gain adjust. Turn all bits on and adjust the gain trimmer, R1, until the output is 9.999847 V. (Full scale is adjusted to 1 LSB less than the nominal full scale of 10.000000 V.) HBE CONTROL LOGIC SER CLR LDAC REF IN REF OUT AD660 SOUT VOUT AGND OUTPUT R2 50Ω R3 16k R4 10k R1 100Ω SPAN/ BIPOLAR OFFSET DGND –VEE +VCC –VEE +VCC +VLL 10V REF 16-BIT LATCH 16-BIT DAC 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 10kΩ 10kΩ 10.05kΩ DB1/DB9/ DATADIR 11 LBE/ CLEAR SELECT DB0/ DB8/ SIN CS DB7/ DB15 5 12 14 16-BIT LATCH Figure 9. 0 V to 10 V Unipolar Voltage Output with Gain and Offset Adjustment |
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