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AD5340BRUZ1 Datasheet(PDF) 8 Page - Analog Devices |
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AD5340BRUZ1 Datasheet(HTML) 8 Page - Analog Devices |
8 / 28 page AD5330/AD5331/AD5340/AD5341 Rev. A | Page 8 of 28 BUFFER 10-BIT DAC DAC REGISTER INPUT REGISTER POWER-DOWN LOGIC DB8 DB7 DB0 .. CS WR CLR LDAC VREF VDD VOUT PD GND AD5331 POWER-ON RESET RESET 10 9 7 6 13 20 1 DB9 2 GAIN 8 3 12 4 11 5 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 LDAC GAIN WR CS GND VREF VOUT CLR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD PD TOP VIEW (Not to Scale) AD5331 10-BIT DB8 DB9 Figure 5. AD5331 Functional Block Diagram Figure 6. AD5331 Pin Configuration Table 6. AD5331 Pin Function Descriptions Pin No. Mnemonic Description 1 DB8 Parallel Data Input. 2 DB9 Most Significant Bit of Parallel Data Input. 3 VREF Unbuffered Reference Input. 4 VOUT Output of DAC. Buffered output with rail-to-rail operation. 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. 9 CLR Active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 13 to 20 DB0 to DB7 Eight Parallel Data Inputs. |
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