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TC7109IJL Datasheet(PDF) 8 Page - Microchip Technology |
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TC7109IJL Datasheet(HTML) 8 Page - Microchip Technology |
8 / 32 page TC7109/A DS21456D-page 8 2002-2012 Microchip Technology Inc. 3.0 DETAILED DESCRIPTION (All Pin Designations Refer to 40-Pin DIP.) 3.1 Analog Section The Typical Application diagram on page 3 shows a block diagram of the analog section of the TC7109A. The circuit will perform conversions at a rate deter- mined by the clock frequency (8192 clock periods per cycle), when the RUN/HOLD input is left open or connected to V+. Each measurement cycle is divided into four phases, as shown in Figure 3-1. They are: (1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference De-integrate (DE), and (4) Zero Integrator (ZI). 3.1.1 AUTO-ZERO PHASE The buffer and the integrator inputs are disconnected from input high and input low and connected to analog common. The reference capacitor is charged to the ref- erence voltage. A feedback loop is closed around the system to charge the auto-zero capacitor, CAZ, to com- pensate for offset voltage in the buffer amplifier, inte- grator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. The offset referred to the input is less than 10 V. 3.1.2 SIGNAL INTEGRATE PHASE The buffer and integrator inputs are removed from com- mon and connected to input high and input low. The auto-zero loop is opened. The auto-zero capacitor is placed in series in the loop to provide an equal and opposite compensating offset voltage. The differential voltage between input high and input low is integrated for a fixed time of 2048 clock periods. At the end of this phase, the polarity of the integrated signal is determined. If the input signal has no return to the converter’s power supply, input low can be tied to analog common to establish the correct Common mode voltage. 3.1.3 DE-INTEGRATE PHASE Input high is connected across the previously charged reference capacitor and input low is internally connected to analog common. Circuitry within the chip ensures the capacitor will be connected with the correct polarity to cause the integrator output to return to the zero crossing (established by auto-zero), with a fixed slope. The time, represented by the number of clock periods counted for the output to return to zero, is proportional to the input signal. 3.1.4 ZERO INTEGRATOR PHASE The ZI phase only occurs when an input over range condition exists. The function of the ZI phase is to eliminate residual charge on the integrator capacitor after an over range measurement. Unless removed, the residual charge will be transferred to the auto-zero capacitor and cause an error in the succeeding conversion. The ZI phase virtually eliminates hysteresis, or “cross- talk” in multiplexed systems. An over range input on one channel will not cause an error on the next channel measured. This feature is especially useful in thermo- couple measurements, where unused (or broken thermocouple) inputs are pulled to the positive supply rail. During ZI, the reference capacitor is charged to the ref- erence voltage. The signal inputs are disconnected from the buffer and integrator. The comparator output is connected to the buffer input, causing the integrator output to be driven rapidly to 0V (Figure 3-1). The ZI phase only occurs following an over range and lasts for a maximum of 1024 clock periods. 3.1.5 DIFFERENTIAL INPUT The TC7109A has been optimized for operation with analog common near digital ground. With +5V and -5V power supplies, a full ±4V full scale integrator swing maximizes the analog section’s performance. A typical CMRR of 86dB is achieved for input differen- tial voltages anywhere within the typical Common mode range of 1V below the positive supply, to 1.5V above the negative supply. However, for optimum per- formance, the IN HI and IN LO inputs should not come within 2V of either supply rail. Since the integrator also swings with the Common mode voltage, care must be exercised to ensure the integrator output does not sat- urate. A worst-case condition is near a full scale nega- tive differential input voltage with a large positive Common mode voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode volt- age. In such cases, the integrator swing can be reduced to less than the recommended ±4V full scale value, with some loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. |
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