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ADF7901BRUZ1 Datasheet(PDF) 4 Page - Analog Devices |
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ADF7901BRUZ1 Datasheet(HTML) 4 Page - Analog Devices |
4 / 12 page ADF7901 Rev. A | Page 4 of 12 Parameter Min Typ Max Unit Comments/Conditions PHASE-LOCKED LOOP VCO Gain 30 MHz/V At 384 MHz Spurious3, 7 100 kHz loop BW Integer Boundary –45 −23 dBc Reference −70 −23 dBc Harmonics3 Second Harmonic VDD = 3.0 V −24 −21 dBc Third Harmonic VDD = 3.0 V −14 −11 dBc All Other Harmonics −18 dBc REFERENCE INPUT Crystal Reference 9.8304 MHz Crystal ESR8 80 Ω POWER AMPLIFIER PA Output Impedance 97 Ω + 6.4 pF At 384 MHz TIMING INFORMATION Crystal Oscillator to PLL Lock3 2 3 ms PA Enable to PA Ready–PLL Settle9 100 250 μs TEMPERATURE RANGE (TA) 0 50 °C 1 Operating temperature range is 0°C to 50°C. 2 Frequency Deviation = 58 × (9.8304 MHz)/214. Error in the crystal is reflected in variation in the desired deviation. 3 Not production tested; based on characterization. 4 The output power can be varied in both ASK/FSK mode by altering the relevant external resistor. 5 Measured using spectrum analyzer, 1 MHz span, 100 kHz RBW, maximum hold enabled. 6 Maximum power-down current specification applies for the OSC2 pin grounded. 7 Measured >461.9 kHz away from channel. 8 Maximum recommended crystal ESR. The crystal oscillator works with crystals with higher ESR, but this results in longer power-up times. 9 This specification refers to the time taken for the PLL to regain lock after the PA has been enabled. The PA is should only be enabled after the PLL has settled to the correct frequency. |
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