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SST25PF080B-80-4C-S2AE Datasheet(PDF) 6 Page - Microchip Technology |
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SST25PF080B-80-4C-S2AE Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 32 page  SST25PF080B DS25134A-page 6 2012 Microchip Technology Inc. 4.4.1 BUSY The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. 4.4.2 WRITE ENABLE LATCH (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write- Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: • Power-up • Write-Disable (WRDI) instruction completion • Byte-Program instruction completion • Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address • Sector-Erase instruction completion • Block-Erase instruction completion • Chip-Erase instruction completion • Write-Status-Register instruction completion • Program SID instruction completion • Lockout SID instruction completion 4.4.3 AUTO ADDRESS INCREMENT (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI pro- gramming mode or Byte-Program mode. The default at power up is Byte-Program mode. 4.4.4 SECURITY ID STATUS (SEC) The Security ID Status (SEC) bit indicates when the Security ID space is locked to prevent a Write com- mand. The SEC is ‘1’ after the host issues a Lockout SID command. Once the host issues a Lockout SID command, the SEC can never be reset to ‘0’. 4.4.5 BLOCK PROTECTION (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table 4-3, to be software protected against any memory Write (Pro- gram or Erase) operation. The Write-Status-Register (WRSR) instruction is used to program the BP2, BP1 and BP0 bits as long as WP# is high or the Block-Pro- tect-Lock (BPL) bit is 0. Chip-Erase can only be exe- cuted if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to 1. 4.4.6 BLOCK PROTECTION LOCK-DOWN (BPL) WP# pin driven low (VIL), enables the Block-Protection- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power- up, the BPL bit is reset to 0. TABLE 4-3: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25PF080B1 1. X = Don’t Care (RESERVED) default is ‘0’ Protection Level Status Register Bit2 2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected) Protected Memory Address BP2 BP1 BP0 8 Mbit None 0 0 0 None Upper 1/16 0 0 1 F0000H-FFFFFH Upper 1/8 0 1 0 E0000H-FFFFFH Upper 1/4 0 1 1 C0000H-FFFFFH Upper 1/2 1 0 0 80000H-FFFFFH All Blocks 1 0 1 00000H-FFFFFH All Blocks 1 1 0 00000H-FFFFFH All Blocks 1 1 1 00000H-FFFFFH |
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