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5CEBA9F23C7N Datasheet(PDF) 5 Page - Altera Corporation |
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5CEBA9F23C7N Datasheet(HTML) 5 Page - Altera Corporation |
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5 / 58 page  Electrical Characteristics Page 5 June 2013 Altera Corporation Cyclone V Device Datasheet Table 4 lists the transceiver power supply recommended operating conditions for Cyclone V GX and GT devices. Table 5 lists the steady-state voltage values expected from Cyclone V system-on-a-chip (SoC) FPGA with ARM®-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. tRAMP (4) Power supply ramp time Standard POR 200 µs — 100 ms — Fast POR 200 µs — 4 ms — Notes to Table 3: (1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO is 3.3 V. (2) PLL digital voltage is regulated from VCCA_FPLL. (3) If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. The power-on reset (POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT stays low. (4) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP specifications for fast POR when HPS_PORSEL = 1. Table 3. Recommended Operating Conditions for Cyclone V Devices—Preliminary (Part 2 of 2) Symbol Description Condition Minimum Typical Maximum Unit Table 4. Transceiver Power Supply Operating Conditions for Cyclone V GX and GT Devices—Preliminary Symbol Description Minimum Typical Maximum Unit VCCH_GXBL Transceiver high voltage power (left side) 2.375 2.5 2.625 V VCCE_GXBL (1), (2) Transmitter and receiver power (left side) 1.07/1.17 1.1/1.2 1.13/1.23 V VCCL_GXBL (1), (2) Clock network power (left side) 1.07/1.17 1.1/1.2 1.13/1.23 V Notes to Table 4: (1) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (2) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144Gbps (Cyclone V GT devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices (1)—Preliminary (Part 1 of 2) Symbol Description Minimum Typical Maximum Unit VCC_HPS HPS core voltage and periphery circuitry power supply 1.07 1.1 1.13 V VCCPD_HPS (2) HPS I/O pre-driver (3.3 V) power supply 3.135 3.3 3.465 V HPS I/O pre-driver (3.0 V) power supply 2.85 3.0 3.15 V HPS I/O pre-driver (2.5 V) power supply 2.375 2.5 2.625 V VCCIO_HPS HPS I/O buffers (3.3 V) power supply 3.135 3.3 3.465 V HPS I/O buffers (3.0 V) power supply 2.85 3.0 3.15 V HPS I/O buffers (2.5 V) power supply 2.375 2.5 2.625 V HPS I/O buffers (1.8 V) power supply 1.71 1.8 1.89 V HPS I/O buffers (1.5 V) power supply 1.425 1.5 1.575 V HPS I/O buffers (1.2 V) power supply 1.14 1.2 1.26 V |
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