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MAX17059 Datasheet(PDF) 2 Page - Maxim Integrated Products |
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MAX17059 Datasheet(HTML) 2 Page - Maxim Integrated Products |
2 / 16 page MAX17058/MAX17059 1-Cell/2-Cell Li+ ModelGauge ICs 2 Maxim Integrated CELL to GND.........................................................-0.3V to +12V All Pins Excluding CELL to GND ............................-0.3V to +6V Continuous Sink Current, SDA, ALRT ................................20mA Operating Temperature Range.......................... -40NC to +85NC Storage Temperature Range............................ -55NC to +125NC Lead Temperature (TDFN only) (soldering, 10s) ...........+300NC Soldering Temperature (reflow) ......................................+260NC ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (2.5V < VDD < 4.5V, -20NC < TA < +70NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) ELECTRICAL CHARACTERISTICS (I2C INTERFACE) (2.5V < VDD < 4.5V, -20NC < TA < +70NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD (Note 2) 2.5 4.5 V Fuel-Gauge SOC Reset (VRESET Register) VRST Configuration range, in 40mV steps 2.28 3.48 V Trimmed at 3V 2.85 3.0 3.15 V Data I/O Pins SCL, SDA, ALRT (Note 2) -0.3 +5.5 V Supply Current IDD0 Sleep mode, TA < +50NC 0.5 2 F A IDD1 Active mode 23 40 Time Base Accuracy tERR Active mode (Note 3) -3.5 Q 1 +3.5 % ADC Sample Period Active mode 250 ms Voltage Error VERR VCELL = 3.6V, TA = +25NC (Note 4) -7.5 +7.5 mV/cell -20NC < TA < +70NC -20 +20 Voltage-Measurement Resolution 1.25 mV/cell Voltage-Measurement Range MAX17058: VDD pin 2.5 5 V MAX17059: CELL pin 5 10 SDA, SCL, QSTRT Input Logic-High VIH 1.4 V SDA, SCL, QSTRT Input Logic-Low VIL 0.5 V SDA, ALRT Output Logic-Low VOL IOL = 4mA 0.4 V SDA, SCL Bus Low-Detection Current IPD VSDA = VSCL = 0.4V (Note 5) 0.2 0.4 F A Bus Low-Detection Timeout tSLEEP (Note 6) 1.75 2.5 s PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 7) 0 400 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 F s START Condition (Repeated) Hold Time tHD:STA (Note 8) 0.6 F s Low Period of SCL Clock tLOW 1.3 F s |
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