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MAX17597 Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX17597 Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 23 page MAX17595/MAX17596/MAX17597 Peak-Current-Mode Controllers for Flyback and Boost Regulators 9 Maxim Integrated Pin Description Pin Configuration PIN NAME FUNCTION 1, 12 N.C. No Connection 2 SLOPE Slope Compensation Input. A resistor, RSLOPE, connected from SLOPE to SGND programs the amount of slope compensation with reference-voltage soft-start mode. Connecting this pin to SGND enables duty-cycle soft-start with default slope compensation of 50mV/Fs. Setting VSLOPE > 4V enables reference voltage soft-start with default slope compensation of 50mV/Fs. 3 RT Switching Frequency Programming Resistor Connection. Connect resistor RRT from RT to SGND to set the PWM switching frequency. 4 DITHER/SYNC Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency operation, connect a capacitor from DITHER to SGND, and a resistor from DITHER to RT. To synchronize the internal oscillator to the externally applied frequency (MAX17595/MAX17596 only), connect DITHER/SYNC to the synchronization pulse. 5 COMP Transconductance Amplifier Output. Connect the frequency compensation network between COMP and SGND. 6 FB Transconductance Amplifier Inverting Input 7 SS Soft-Start Capacitor Pin for Flyback Regulator. Connect a capacitor CSS from SS to SGND to set the soft-start time interval. 8 SGND Signal Ground. Connect SGND to the signal ground plane. 9 CS Current-Sense Input. Peak-current-limit trip voltage is 300mV (typ). 10 PGND Power Ground. Connect PGND to the power ground plane. 11 NDRV External Switching nMOS Gate-Driver Output 15 16 14 13 5 6 7 8 13 VIN 4 12 10 9 EN/ UVLO OVI EP SGND SS FB COMP 2 11 VDRV TQFN MAX17595 MAX17596 TOP VIEW + 15 16 14 13 5 6 7 8 13 VIN 4 12 10 9 EN/UVLO OVI EP SGND SS FB COMP 2 11 VDRV TQFN MAX17597 + |
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