LOAD CURRENT (A)

STABLE REGION

0

1

2

3

.001

.01

0.1

1.0

10

LP3876-ADJ

SNVS245C – SEPTEMBER 2003 – REVISED APRIL 2013

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Application Hints

SETTING THE OUTPUT VOLTAGE

The output voltage is set using the resistors R1 and R2 (see Typical Application Circuit). The output is also

dependent on the reference voltage (typically 1.216V) which is measured at the ADJ pin. The output voltage is

given by the equation:

(1)

This equation does not include errors due to the bias current flowing in the ADJ pin which is typically about 10

nA. This error term is negligible for most applications. If R1 is > 100k

Ω , a small error may be introduced by the

ADJ bias current.

The tolerance of the external resistors used contributes a significant error to the output voltage accuracy, with 1%

resistors typically adding a total error of approximately 1.4% to the output voltage (this error is in addition to the

TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW

As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating

voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may

momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V

are not affected by this behavior.

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are required to assure stability. these capacitors must be

correctly selected for proper performance.

INPUT CAPACITOR: An input capacitor of at least 1µF is required. Ceramic or Tantalum may be used, and

capacitance may be increased without limit

OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 cm from

the device and connected directly to the output and ground pins using traces which have no other currents

flowing through them (see PCB Layout section).

The minimum value of the output capacitance that can be used for stable full-load operation is 10 µF, but it may

be increased without limit. The output capacitor must have an ESR value as shown in the stable region of the

curve (below).

Figure 21. ESR Curve

capacitance depends on the value selected for R1 (see TYPICAL APPLICATION CIRCUIT). The capacitor

should be selected such that the zero frequency as given by the equation shown below is approximately 45 kHz:

Fz = 45,000 = 1 / ( 2 x

(2)

A good quality ceramic with X5R or X7R dielectric should be used for this capacitor.

8

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