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THS1030 Datasheet(PDF) 6 Page - Texas Instruments |
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THS1030 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 39 page THS1030 3V TO 5.5V, 10BIT, 30 MSPS CMOS ANALOGTODIGITAL CONVERTER SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference, TA = Tmin to Tmax (unless otherwise noted) (continued) clock PARAMETER MIN TYP MAX UNIT tc Clock cycle 33 ns tw(CKH) Pulse duration, clock high 15 16.5 110 ns tw(CKL) Pulse duration, clock low 15 16.5 110 ns td(o) Clock to data valid, delay time 25 ns td(DZ) Output disable to Hi-Z output, disable time 20 ns td(DEN) Output enable to output valid, enable time 20 ns Pipeline latency 3 Cycles td(AP) Aperture delay time 4 ns Aperture uncertainty (jitter) 2 ps power supply (See Note 7) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Operating supply current AVDD = DVDD = 3 V, MODE = AVDD 29 40 mA PD Power dissipation AVDD = DVDD = 3 V 87 120 mW PD Power dissipation AVDD = DVDD = 5 V 150 mW PD(STBY) Standby power AVDD = DVDD = 3 V, MODE = AVDD 3 5 mW NOTES: 7. Mode and REFSENSE are set to AVDD. The internal reference buffer is powered up to buffer the externally applied 0.5 V REFBS and 2.5 V REFTS. 1.5 VDC is applied at AIN while converting data at 30 MSPS. |
Similar Part No. - THS1030_13 |
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Similar Description - THS1030_13 |
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