TLK1501

0.6 TO 1.5 GBPS TRANSCEIVER

SLLS428F − JUNE 2000 − REVISED JANUARY 2004

9

POST OFFICE BOX 655303

detailed description (continued)

IDLE insertion

The encoder inserts the IDLE character set when no payload data is available to be sent. IDLE consists of a

K28.5 (BC) code and either a D5.6 (C5) or a D16.2 (50) character. The K28.5 character is defined by IEEE802.3z

as a pattern consisting of 0011111010 ( a negative number beginning disparity) with the 7 MSBs (0011111),

referred to as the comma character. Since data is transmitted to the TLK1501 20 in a GTX_CLK cycle. The

comma character is converted to two 10-bit wide code.

PRBS generator

forced high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter

input register. Data from the normal input source is ignored during the PRBS mode. The PRBS pattern is then

fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent

to a BERT (bit error rate tester), the receiver of another TLK1501, or can be looped back to the receive input.

Since the PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be

captured and checked for errors by a BERT.

parallel-to-serial

The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the two parallel 8-bit/10-bit

encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of

the internally generated bit clock, which is 10 times the GTX_CLK input frequency. The LSB (TXD0) is

transmitted first.

high-speed data output

The high-speed data output driver consists of a current-mode logic (CML) differential pair that can be optimized

for a particular transmission line impedance and length. The line can be directly-coupled or ac-coupled. Refer

to Figure 15 and Figure 16 for termination details.

receive interface

The receiver portion of the TLK1501 accepts 8-bit/10-bit encoded differential serial data. The interpolator and

clock recovery circuit locks to the data stream and extract the bit rate clock. This recovered clock is used to

retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit

decoded and output on a 16-bit wide parallel bus synchronized to the extracted receive clock.

receive data bus

The receive bus interface drives 16-bit wide single-ended TTL parallel data at the RXD[0:15] terminals. Data

is valid on the rising edge of the RX_CLK when the RX_DV/LOS is asserted high and the RX_ER is deasserted

low. The RX_CLK is used as the recovered word clock. The data, enable, and clock signals are aligned as shown

in Figure 4. Detailed timing information can be found in the switching characteristics table.

RX_CLK

RXDn, RX_DV, RX_ER

tsu

th

Figure 4. Receive Timing Waveform