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TMS320C6747BZKB3 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6747BZKB3 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 227 page  TMS320C6745, TMS320C6747 SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013 www.ti.com • NOR (8-/16-Bit-Wide Data) Device Only • NAND (8-/16-Bit-Wide Data) – End Point 0 (Control) • 16-Bit SDRAM With 128MB Address – End Points 1,2,3,4 (Control, Bulk, Interrupt or Space (C6747 Only) ISOC) Rx and Tx – EMIFB • Three Multichannel Audio Serial Ports: • 32-Bit or 16-Bit SDRAM With 256MB – C6747 supports 3 McASPs Address Space (C6747) – C6745 supports 2 McASPs • 16-Bit SDRAM With 128MB Address – Six Clock Zones and 28 Serial Data Pins Space (C6745) – Supports TDM, I2S, and Similar Formats • Three Configurable 16550 type UART Modules: – DIT-Capable (McASP2) – UART0 With Modem Control Signals – FIFO buffers for Transmit and Receive – Autoflow control signals (CTS, RTS) on • 10/100 Mb/s Ethernet MAC (EMAC): UART0 only – IEEE 802.3 Compliant (3.3-V I/O Only) – 16-byte FIFO – RMII Media Independent Interface – 16x or 13x Oversampling Option – Management Data I/O (MDIO) Module • LCD Controller (C6747 Only) • Real-Time Clock With 32 KHz Oscillator and • Two Serial Peripheral Interfaces (SPI) Each Separate Power Rail (C6747 Only) With One Chip-Select • One 64-Bit General-Purpose Timer • Multimedia Card (MMC)/Secure Digital (SD) (Configurable as Two 32-Bit Timers) Card Interface with Secure Data I/O (SDIO) • One 64-bit General-Purpose/Watchdog Timer • Two Master/Slave Inter-Integrated Circuit (I2C (Configurable as Two 32-bit General-Purpose Bus™) Timers) • One Host-Port Interface (HPI) With 16-Bit-Wide • Three Enhanced Pulse Width Modulators Muxed Address/Data Bus For High Bandwidth (eHRPWM): (C6747 only) – Dedicated 16-Bit Time-Base Counter With • Programmable Real-Time Unit Subsystem Period And Frequency Control (PRUSS) – 6 Single Edge, 6 Dual Edge Symmetric or 3 – Two Independent Programmable Realtime Dual Edge Asymmetric Outputs Unit (PRU) Cores – Dead-Band Generation • 32-Bit Load/Store RISC architecture – PWM Chopping by High-Frequency Carrier • 4K Byte instruction RAM per core – Trip Zone Input • 512 Bytes data RAM per core • Three 32-Bit Enhanced Capture Modules • PRU Subsystem (PRUSS) can be disabled (eCAP): via software to save power – Configurable as 3 Capture Inputs or 3 – Standard power management mechanism Auxiliary Pulse Width Modulator (APWM) • Clock gating outputs • Entire subsystem under a single PSC – Single Shot Capture of up to Four Event clock gating domain Time-Stamps – Dedicated interrupt controller • Two 32-Bit Enhanced Quadrature Encoder – Dedicated switched central resource Pulse Modules (eQEP) • USB 1.1 OHCI (Host) With Integrated PHY • C6747 Device: (USB1) (C6747 Only) – 256-Ball Pb-Free Plastic Ball Grid Array • USB 2.0 OTG Port With Integrated PHY (USB0) (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch – USB 2.0 High-/Full-Speed Client (C6747) • C6745 Device – USB 2.0 Full-Speed Client (C6745) – 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch – USB 2.0 High-/Full-/Low-Speed Host (C6747) • Commercial, Industrial, Extended, or – USB 2.0 Full-/Low-Speed Host (C6745) Automotive Temperature – High-speed Functionality Available on C6747 2 TMS320C6745/6747 Fixed/Floating-Point Digital Signal Processor Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C6745 TMS320C6747 |
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