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TMS320F241FNS Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320F241FNS Datasheet(HTML) 9 Page - Texas Instruments |
9 / 122 page TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions - F243 PGE Package (Continued) NAME 144 LQFP TYPE† RESET STATE‡ DESCRIPTION NAME NO. TYPE† STATE‡ DESCRIPTION SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS SPISIMO/IOPC2 60 I/O I SPI slave in, master out or GPIO SPISOMI/IOPC3 62 I/O I SPI slave out, master in or GPIO SPICLK/IOPC4 64 I/O I SPI clock or GPIO SPISTE/IOPC5 66 I/O I SPI slave transmit enable (optional) or GPIO SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS SCITXD/IOPA0 56 I/O I SCI asynchronous serial port transmit data or GPIO SCIRXD/IOPA1 58 I/O I SCI asynchronous serial port receive data or GPIO CONTROLLER AREA NETWORK (CAN) CANTX/IOPC6 115 I/O I CAN transmit data or GPIO CANRX/IOPC7 113 I/O I CAN receive data or GPIO INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS RS 19 I/O I Device reset. RS causes the F243/241 to terminate execution and sets PC = 0. When RS is brought to a high level, execution begins at location zero of program memory. RS affects (or sets to zero) various registers and status bits. When the watchdog timer overflows, it initiates a system reset pulse that is reflected on the RS pin. This pulse is eight clock cycles wide. NMI§ 79 I I Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state of the INTM bit of the status register. NMI is (falling) edge- and low-level-sensitive. To be recognized by the core, this pin must be kept low for at least one clock cycle after the falling edge. XINT1/IOPA2 83 I/O I External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge- sensitive. To be recognized by the core, these pins must be kept high/low for at least one clock cycle after the edge. The edge polarity is programmable. XINT2/ADCSOC/IOPD1 81 I/O I External user interrupt 2. External “start-of-conversion” input for ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be recognized by the core, these pins must be kept high/low for at least one clock cycle after the edge. The edge polarity is programmable. MP/MC 43 I I Microprocessor/Microcomputer mode select. If this pin is low during reset, the device is put in microcomputer mode and program execution begins at 0000h of internal program memory (flash EEPROM). A high value during reset puts the device in microprocessor mode and program execution begins at 0000h of external program memory. ( ↓) READY 44 I I READY is pulled low to add wait states for external accesses. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready, it pulls the READY pin low. The processor waits one cycle and checks READY again. Note that the processor performs READY-detection if at least one software wait state is programmed. To meet the external READY timings, the wait-state generator control register (WSGR) should be programmed for at least one wait state. ( ↑) † I = input, O = output, Z = high impedance ‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is an output, its level at reset is indicated. § At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS is enabled. NOTE: Bold, italicized pin names indicate pin function after reset. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is 150 µA.) |
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