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TMS320C6747DZKBT3R Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320C6747DZKBT3R Datasheet(HTML) 11 Page - Texas Instruments |
11 / 227 page Instruction Fetch C674x Fixed/Floating Point CPU Register File A Register File B Cache Control Memory Protect Bandwidth Mgmt L1P 256 Cache Control Memory Protect Bandwidth Mgmt L1D 64 64 8 x 32 32K Bytes L1D RAM/ Cache 32K Bytes L1P RAM/ Cache 256 Cache Control Memory Protect Bandwidth Mgmt L2 256K Bytes L2 RAM 256 Boot ROM 256 CFG MDMA SDMA EMC Power Down Interrupt Controller IDMA 256 256 256 256 256 64 High Performance Switch Fabric 64 64 64 Configuration Peripherals Bus 32 TMS320C6745, TMS320C6747 www.ti.com SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013 2.3 DSP Subsystem The DSP Subsystem includes the following features: • C674x DSP CPU • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 256KB Unified Mapped RAM/Cache (L2) • Boot ROM (cannot be used for application code) • Little endian Figure 2-1. C674x Megamodule Block Diagram Copyright © 2008–2013, Texas Instruments Incorporated Device Overview 11 Submit Documentation Feedback Product Folder Links: TMS320C6745 TMS320C6747 |
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