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TMX320F28232ZJZA Datasheet(PDF) 8 Page - Texas Instruments |
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TMX320F28232ZJZA Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 199 page  TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6-5 Clocking and Nomenclature (100-MHz Devices) ........................................................................... 125 6-6 Input Clock Frequency ......................................................................................................... 126 6-7 XCLKIN Timing Requirements – PLL Enabled ............................................................................. 126 6-8 XCLKIN Timing Requirements – PLL Disabled ............................................................................ 126 6-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 126 6-10 Power Management and Supervisory Circuit Solutions ................................................................... 128 6-11 Reset (XRS) Timing Requirements .......................................................................................... 130 6-12 General-Purpose Output Switching Characteristics ........................................................................ 131 6-13 General-Purpose Input Timing Requirements .............................................................................. 132 6-14 IDLE Mode Timing Requirements ........................................................................................... 134 6-15 IDLE Mode Switching Characteristics ....................................................................................... 134 6-16 STANDBY Mode Timing Requirements ..................................................................................... 135 6-17 STANDBY Mode Switching Characteristics ................................................................................ 135 6-18 HALT Mode Timing Requirements ........................................................................................... 137 6-19 HALT Mode Switching Characteristics ...................................................................................... 137 6-20 ePWM Timing Requirements ................................................................................................. 139 6-21 ePWM Switching Characteristics ............................................................................................ 139 6-22 Trip-Zone Input Timing Requirements ...................................................................................... 139 6-23 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz) .............................................. 140 6-24 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 140 6-25 eCAP Switching Characteristics ............................................................................................. 140 6-26 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 141 6-27 eQEP Switching Characteristics ............................................................................................. 141 6-28 External ADC Start-of-Conversion Switching Characteristics ............................................................. 142 6-29 External Interrupt Timing Requirements .................................................................................... 142 6-30 External Interrupt Switching Characteristics ................................................................................ 142 6-31 I2C Timing ...................................................................................................................... 143 6-32 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 144 6-33 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 146 6-34 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 148 6-35 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 150 6-36 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 151 6-37 XINTF Clock Configurations .................................................................................................. 154 6-38 External Interface Read Timing Requirements ............................................................................. 156 6-39 External Interface Read Switching Characteristics ......................................................................... 156 6-40 External Interface Write Switching Characteristics ......................................................................... 158 6-41 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ................................... 160 6-42 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 160 6-43 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 160 6-44 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 160 6-45 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 163 6-46 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 163 6-47 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 163 6-48 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 167 6-49 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 168 6-50 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 169 6-51 ADC Power-Up Delays ......................................................................................................... 170 6-52 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 170 8 List of Tables Copyright © 2007–2012, Texas Instruments Incorporated |
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