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TPS54672PWPR Datasheet(PDF) 9 Page - Texas Instruments |
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TPS54672PWPR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 20 page  TPS54672 SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 www.ti.com 9 OUTPUT FILTER The output filter is composed of a 0.56- µH Coilcraft inductor (D01813P−561HC) and two 150- µF Cornell Dublier capacitors (ESRD151M06R). The inductor is a low dc resistance type. The capacitors used are 4 V POSCAP types with a maximum ESR of 0.040 Ω. PCB LAYOUT Figure 10 shows a generalized PCB layout guide for the TPS54672. The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR ceramic bypass capacitor. Minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54672 ground pins. The minimum recommended bypass capacitance is 10 µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND pins. The TPS54672 has two internal grounds (analog and power). Inside the TPS54672 the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between the two grounds can degrade the performance of the TPS54672, particularly at higher output currents. Ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground traces are recommended. There should be an area of ground on the top layer under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them to the ground area under the device as shown. The only components that should tie directly to the power ground plane are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54672. Use a separate wide trace for the analog ground signal path. This analog ground should be used for the voltage set point divider, timing resistor RT, and bias capacitor grounds. Connect this trace directly to AGND (pin 1). The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching node, the inductor should be located very close to the PH pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout, and PGND as small as practical. Place the compensation components from the VOUT trace to the VSENSE, and COMP pins. Do not place these components too close to the PH trace. Due to the size of the IC package and the device pin out, the components must be routed somewhat close, however maintaining as much separation as possible while still keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If an RT resistor is used, connect it to this trace as well. |
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