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DGS

(TOP VIEW)

DRC

(TOP VIEW)

1

2

3

4

5

10

9

8

7

6

EN

COMP

FB

GND

VOUT

LBO

LBI

ADEN

SW

VBAT

FB

GND

VOUT

VBAT

LBI

COMP

SW

ADEN

EN

LBO

DETAILED DESCRIPTION

Controller Circuit

Synchronous Rectifier

TPS61010, TPS61011

TPS61012, TPS61013

TPS61014, TPS61015, TPS61016

SLVS314D – SEPTEMBER 2000 – REVISED JUNE 2005

Terminal Functions

Terminal

I/O

Description

DRG

DRC

Name

No.

No.

Autodischarge input. The autodischarge function is enabled if this pin is connected to VBAT, it is disabled

ADEN

8

8

I

if ADEN is tied to GND.

COMP

2

2

I

Compensation of error amplifier. Connect an R/C/C network to set frequency response of control loop.

1

I

Chip-enable input. The converter is switched on if this pin is set high, it is switched off if this pin is

EN

1

connected to GND.

Feedback input for adjustable output voltage version TPS61010. Output voltage is programmed

FB

3

3

I

depending on the output voltage divider connected there. For the fixed output voltage versions, leave

FB-pin unconnected.

GND

4

4

Ground

Low-battery detector input. A low battery warning is generated at LBO when the voltage on LBI drops

LBI

9

9

I

below the threshold of 500 mV. Connect LBI to GND or VBAT if the low-battery detector function is not

used. Do not leave this pin floating.

Open-drain low-battery detector output. This pin is pulled low if the voltage on LBI drops below the

LBO

10

10

O

threshold of 500 mV. A pullup resistor must be connected between LBO and VOUT.

SW

7

7

I

Switch input pin. The inductor is connected to this pin.

VOUT

5

5

O

Output voltage. Internal resistor divider sets regulated output voltage in fixed output voltage versions.

VBAT

6

6

I

Supply pin

The device is based on a current-mode control topology using a constant frequency pulse-width modulator to

regulate the output voltage. The controller limits the current through the power switch on a pulse by pulse basis.

The current-sensing circuit is integrated in the device, therefore, no additional components are required. Due to

the nature of the boost converter topology used here, the peak switch current is the same as the peak inductor

current, which will be limited by the integrated current limiting circuits under normal operating conditions.

The control loop must be externally compensated with an R-C-C network connected to the COMP-pin.

The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier. There

rectification, the power conversion efficiency reaches 95%.

A special circuit is applied to disconnect the load from the input during shutdown of the converter. In conventional

synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in shutdown and

allows current flowing from the battery to the output. This device, however, uses a special circuit to disconnect

the backgate diode of the high-side PMOS and so, disconnects the output circuitry from the source when the

regulator is not enabled (EN = low).

The benefit of this feature for the system design engineer, is that the battery is not depleted during shutdown of

the converter. So, no additional effort has to be made by the system designer to ensure disconnection of the

battery from the output of the converter. Therefore, design performance will be increased without additional costs

and board space.

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