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PI3VDP411LSZBE Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation |
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PI3VDP411LSZBE Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation |
7 / 13 page 7 PS8913D 11/05/08 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Table 5: Differential Input Characteristics for IN_D and RX_IN signals Symbol Parameter Min Nom Max Units Comments Tbit Unit Interval 360 ps Tbit is determined by the display mode. Nom- inal bit rate ranges from 250Mbps to 2.5Gbps per lane. Nominal Tbit at 2.5 Gbps=400ps. 360ps=400ps-10% VRX-DIFFp-p Differential Input Peak to Peak Voltage 0.175 1.200 V VRX-DIFFp-p=2'|VRX-D+ x VRX-D-| Applies to IN_D and RX_IN signals TRX-EYE Minimum Eye Width at IN_D input pair 0.8 Tbit The level shifter may add a maximum of 0.02UI jitter VCM-AC-pp AC Peak Common Mode Input Voltage 100 mV VCM-AC-pp = |VRX-D+ + VRX-D-|/2 - VRX-CM-DC. VRX-CM-DC = DC(avg) of|VRX-D+ + VRX-D-|/2 VCM-AC-pp includes all frequencies above 30 kHz. ZRX-DC 40 50 60 Ω Required IN_D+ as well as IN_D- DC impedance (50 Ω ± 20% tolerance). VRX-Bias 0 2.0 V Intended to limit power-up stress on chipset's PCIE output buffers. ZRX-HIGH-Z 100 k Ω Differential inputs must be in a high im- pedance state when OE# is HIGH. 08-0294 |
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