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PI49FCT3805EQ Datasheet(PDF) 4 Page - Pericom Semiconductor Corporation |
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PI49FCT3805EQ Datasheet(HTML) 4 Page - Pericom Semiconductor Corporation |
4 / 9 page 4 PS8492D 11/13/08 PI49FCT3805D/E 3.3V, 2 x 1:5 CMOS Clock Driver Switching Characteristics over Operating Range Parameters Description Test Conditions (1) 3805D 3805E Units Max. Max. tPLH tPHL Propagation Delay INN to ON CL = 15pF, 133 MHz (3805D) 166 MHz (3805E) 3.0 2.5 tR/tF CLKn Rist/Fall Time 0.8V ~ 2.0V 1.5 1.0 ns tSK(o)(3) Pulse Skew 270 270 ps tSK(p)(3) Output Skew 270 200 tSK(t)(3) Package Skew 550 550 tZL, tZH, tLZ, tHZ Enable/Disable Time 5.2 5.0 ns FMAX Input Frequency 133 166 MHz Switch Position Test Switch Disable LOW Enable LOW 6V Disable HIGH Enable HIGH GND All Other Inputs Open Definitions: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Tests Circuit Note: 1. These parameters are guaranteed by design 2. Series Resistor loading = 33Ω (See Test Circuit) Pulse Generator f = 125MHz D.U.T. 50 Ω 33 Ω CL 15pF VCC Enable/Disable Time Test Set-Up Pulse Generator D.U.T. 500 Ω 33 Ω 50 Ω 500 Ω CL 15pF VCC S 6V 08-0298 |
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