Electronic Components Datasheet Search |
|
FM27C010NE120 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
|
FM27C010NE120 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 10 page 1 www.fairchildsemi.com www.fairchildsemi.com FM27C010 FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM General Description The FM27C010 is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory. It is organized as 128K-words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through 8 Mbit EPROMs. The “Don’t Care” feature during read operations allows memory expansions from 1M to 8M bits with no printed circuit board changes. The FM27C010 can directly replace lower density 28-pin EPROMs by adding an A16 address line and V CC jumper. During the normal read operation PGM and VPP are in a “Don’t Care” state which allows higher order addresses, such as A17, A18, and A19 to be connected without affecting the normal read operation. This allows memory upgrades to 8M bits without hardware changes. The FM27C010 is also offered in a 32-pin plastic DIP with the same upgrade path. The FM27C010 provides microprocessor-based systems exten- sive storage capacity for large portions of operating system and application software. Its 70 ns access time provides no-wait-state operation with high-performance CPUs. The FM27C010 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility. Block Diagram January 2000 The FM27C010 is manufactured using Fairchild’s advanced CMOS AMG™ EPROM technology. The FM27C010 is one member of a high density EPROM Family which range in densities up to 4 Megabit. Features I High performance CMOS — 70 ns access time I Fast turn-off for microprocessor compatibility I Simplified upgrade path —VPP and PGM are “Don’t Care” during normal read operation I Manufacturers identification code I Fast programming I JEDEC standard pin configurations — 32-pin PDIP package — 32-pin PLCC package — 32-pin CERDIP package DS800032-1 © 2000 Fairchild Semiconductor Corporation Output Enable, Chip Enable, and Program Logic Y Decoder X Decoder Output Buffers 1,048,576-Bit Cell Matrix Data Outputs O0 - O7 VCC GND VPP OE PGM CE A0 - A16 Address Inputs |
Similar Part No. - FM27C010NE120 |
|
Similar Description - FM27C010NE120 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |