8

www.fairchildsemi.com

FM93C46A Rev. C.1

SYNCHRONOUS DATA TIMING

CS

SK

DI

DO (Data Read)

DO (Status Read)

Valid Status

Valid

Input

Valid

Input

Valid

Output

Valid

Output

CS

SK

DI

DO

High - Z

Dummy

Bit

1

1

0

A1

A0

0

D1

D0

;;;;;;;;;;;;;;

;;;;;;;;;;;;;;

;;;

;;;

READ CYCLE (READ)

Address

Bits(6/7)

Star t

Bit

Opcode

Bits(2)

93C46A (ORG=1;

A

Address bits patter n -> A5-A4-A3-A2-A1-A0; User defined

93C46A (ORG=0;

A

Address bits patter n -> A6-A5-A4-A3-A2-A1-A0; User defined

A

n

A

n-1

D

n

Timing Diagrams

Address

Bits(6/7)

CS

SK

DI

DO

High - Z

WRITE ENABLE CYCLE (WEN)

Start

Bit

Opcode

Bits(2)

1

0

0

A1

A0

A

n

A

n-1

93C46A (ORG=1;

A

Address bits pattern -> 1-1-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1)

93C46A (ORG=0;

A

Address bits pattern -> 1-1-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1)