67-11

APPLICATIONS CIRCUIT

APPLICATIONS INFORMATION

The above is a partial application circuit for the ZNBG series showing all external components

required for appropriate biasing. The bias circuits are unconditionally stable over the full

temperature range with the associated FETs and gate and drain capacitors in circuit.

allowed to affect other external circuits which may be sensitive to RF interference. They also

serve to suppress any potential RF feedthrough between stages via the ZNBG device. These

capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are

recommended however this is design dependent and any value between 1nF and 100nF could

be used.

negative bias voltage is generated on-chip using an internal oscillator. The required value of

-3 volts. Although this generator is intended purely to bias the external FETs, it can be used to

circuit is not required, its related drain and gate connections may be left open circuit without

affecting the operation of the remaining bias circuits.

The ZNBG devices have been designed to protect the external FETs from adverse operating

conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit

can not exceed the range -3.5V to 1V under any conditions, including powerup and powerdown

transients. Should the negative bias generator be shorted or overloaded so that the drain current

of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid

damage to the FETs by excessive drain current.

ZNBG3210

ZNBG3211