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RC28F128J3F75A Datasheet(PDF) 9 Page - Micron Technology |
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RC28F128J3F75A Datasheet(HTML) 9 Page - Micron Technology |
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9 / 66 page  Jan 2011 Datasheet 208032-03 9 Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 2.0 Functional Overview The J3 65 nm SBC family contains high-density memory organized in any of the following configurations: • 16-MB or 8-MW (128-Mbit), organized as one-hundred-twenty-eight 128-KB erase blocks. • 8-MB or 4-MW (64-Mbit), organized as sixty-four 128-KB erase blocks. • 4-MB or 2-MW (32-Mbit), organized as thirty-two 128-KB erase blocks. These devices can be accessed as 8- or 16-bit words. See Figure 1, “Memory Block Diagram for 32-, 64-, 128-Mbit” on page 11 for further details. A 128-bit Protection Register has multiple uses, including unique flash device identification. The J3 65 nm SBC device includes new security features that were not available on the (previous) 0.13µm versions of the J3 family. These new security features prevent altering of code through different protection schemes that can be implemented, based on user requirements. The J3 65 nm SBC optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. Its Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. The Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system- level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 128-KB blocks typically within one second, independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 256-Byte (x8 mode) or 256-Word (x16 mode) to allow optimum programming performance. By using the Write Buffer data is programmed more efficiently in buffer increments. Memory Blocks are selectively and individually lockable in-system. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (using the Set Block Lock-Bit and Clear Block Lock-Bits commands). |
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