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UCC3921DTR Datasheet(PDF) 7 Page - Texas Instruments |
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UCC3921DTR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 16 page  7 UCC1921 UCC2921 UCC3921 During a fault, CT will charge at a rate determined by the internal charging current and the external timing capaci- tor. Once CT charges to 2.5V, the fault comparator switches and sets the fault latch. Setting of the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with the 1 µA cur- rent source, I2, until 0.5V is reached. Once the voltage at CT reaches 0.5V, the fault latch resets, which re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the fault comparator will close the charging switch causing the cy- cle to repeat. Under a constant fault, the duty cycle is given by: Duty Cycle A IA PL = + 1 36 µ µ Average power dissipation in the pass element is given by: PV I A IA FET FET MAX PL )8/ =• • + 1 36 µ µ Where VFET>>5V IPL can be approximated as: V R FET PL and where IPL>>36µA, the duty cycle can be approxi- mated as : 1µAR V PL FET • Therefore, the maximum average power dissipation in the MOSFET can be approximated by: PV I AR V IMAX A R FET FET MAX PL FET PL )8/ =• • • =• • 1 1 µ µ Notice that in the approximation, VFET cancels, thereby limiting the average power dissipation in the NMOS pass element. Overload Comparator The linear amplifier in the UCC3921 ensures that the output NMOS does not pass more than IMAX (which is VIMAX/RSENSE). In the event the output current exceeds the programmed IMAX by 0.2V/RSENSE, which can only occur if the output FET is not responding to a command from the IC, CT will begin charging with I3, 1mA, and continue to charge to approximately 8V. This allows a constant fault to show up on the SDFLTCH pin, and also since the voltage on CT will continue charging past 2.5V in an overload fault mode, it can be used for detection of output FET failure or to build redundancy into the sys- tem. Determining External Component Values To set RVDD (see Fig. 4) the following must be achieved: V R V RR mA IN VDD min > + + 10 12 2 In order to estimate the minimum timing capacitor, CT, several things must be taken into account. For example, given the schematic in Figure 4 as a possible (and at this point, a standard) application, certain external compo- nent values must be known in order to estimate CTMIN. Now, given the values of COUT, Load, RSENSE,VSS, and the resistors determining the voltage on the IMAX pin, the user can calculate the approximate startup time of the node VOUT. This startup time must be faster than the time it takes for CT to charge to 2.5V (relative to VSS), and is the basis for estimating the minimum value of CT. In order to determine the value of the sense resistor, RSENSE, assuming the user has determined the fault cur- rent, RSENSE can be calculated by: R mV I SENSE FAULT = 50 Next, the variable IMAX must be calculated. IMAX is the maximum current that the UCC3921 will allow through the transistor, M1, and it can be shown that during startup with an output capacitor the power MOSFET, M1, can be modeled as a constant current source of value IMAX where I V R MAX IMAX SENSE = where VIMAX = voltage on pin IMAX. Given this information, calculation of the startup time is now possible via the following: APPLICATION INFORMATION (continued) Figure 4. UDG-96278 |
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