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TAS3004PFBRG4 Datasheet(PDF) 5 Page - Texas Instruments |
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TAS3004PFBRG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 84 page vi List of Illustrations Figure Title Page 1–1 TAS3004 Block Diagram 1–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 TAS3004 Terminal Assignments 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 MSB First, Right-Justified Serial Interface Format—Normal Mode 2–2 . . . . . 2–2I2S Serial Interface Format—Normal Mode 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 MSB Left-Justified Serial Interface Format—Normal Mode 2–4 . . . . . . . . . . . 2–4 MSB First, Right-Justified Serial Interface Format—Monaural ADC Mode, B Left Input Selected 2–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5I2S Serial Interface Format—Monaural ADC Mode, B Left Input Selected 2–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Left Input Selected 2–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 MSB First, Right-Justified Serial Interface Format—Monaural ADC Mode, B Right Input Selected 2–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8I2S Serial Interface Format—Monaural ADC Mode, B Right Input Selected 2–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Right Input Selected 2–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 For Right-/Left-Justified, I2S, and Left-/Left-Justified Serial Protocols 2–11 . . 3–1 Analog Input to the TAS3004 Device 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 VCOM Decoupling Network 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Analog Output With External Amplifier 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 TAS3004 Reference Voltage Filter 3–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 TAS3004 Mix Function 4–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 De-Emphasis Mode Frequency Response 4–3 . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Block Diagram 4–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 TAS3004 Digital Signal Processing Block Diagram 4–6 . . . . . . . . . . . . . . . . . . 5–1 Biquad Cascade Configuration 5–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 Typical I2C Data Transfer Sequence 6–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 TAS3004 Reset Circuit 7–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 Power-Down Timing Sequence 7–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Internal Interface Block Diagram 7–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 ADC Digital Filter Characteristics 8–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 ADC Digital Filter Stopband Characteristics 8–2 . . . . . . . . . . . . . . . . . . . . . . . . 8–3 ADC Digital Filter Passband Characteristics 8–3 . . . . . . . . . . . . . . . . . . . . . . . . 8–4 ADC High Pass Filter Characteristics 8–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5 DAC Filter Overall Frequency Characteristics 8–4 . . . . . . . . . . . . . . . . . . . . . . . |
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