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UCC3921DG4 Datasheet(PDF) 3 Page - Texas Instruments

Part # UCC3921DG4
Description  Latchable Negative Floating Hot Swap Power Manager
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

UCC3921DG4 Datasheet(HTML) 3 Page - Texas Instruments

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3
UCC1921
UCC2921
UCC3921
ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = 0°C to 70°C for the UCC3921 and –40°C to 85°C
for the UCC2921, and –55°C to 125°C for the UCC1921; IVDD = 2mA, CT = 1nF (the minimum allowable value), there is no
resistor connected between the SDFLTCH and VSS pins. TA =TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output Section
Output High Voltage
IOUT = 0mA
8.5
10
V
IOUT = –1mA
6
8
V
Output Low Voltage
IOUT = 0mA, VSENSE –VIMAX = 100mV
0
10
mV
IOUT = 2mA, VSENSE –VIMAX = 100mV
200
600
mV
Linear Amplifier Section
Sense Control Voltage
VIMAX = 100mV
85
100
115
mV
VIMAX = 400mV
370
400
430
mV
Input Bias
50
500
nA
Power Limiting Section
VSENSE Regulator Voltage
IPL =64µA
4.35
4.85
5.35
V
Duty Cycle Control
IPL =64µA
0.6
1.2
1.7
%
IPL = 1mA
0.045
0.1
0.17
%
Overload Section
Delay to Output
Note 1
300
500
ns
Output Sink Current
VSENSE –VIMAX = 300mV
40
100
mA
Threshold
Relative to IMAX
140
200
260
mV
Shutdown/Fault/Latch Section
Shutdown Threshold
3
5
VDD+1
V
Input Current
VSDFLTCH = 5V
50
110
250
µA
Filter Delay Time (Delay to Output)
250
500
1000
µs
Fault Output High
6
9.5
V
ISDFLTCH = –100µA
5
8.5
V
Fault Output Low
010
mV
Output Duty Cycle
Fault Condition, IPL = 0
1.7
2.7
3.7
%
ISDFLTCH = –100µA, Fault Condition, IPL =0
0
%
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
CT: A capacitor is connected to this pin in order to set
the fault time. The fault time must be longer than the time
to charge external load capacitance. The
fault time is
defined as:
T
C
I
FAULT
T
CH
=
2
where ICH =36
µA+IPL, and IPL is the current into the
power limit pin. Once the maximum fault time is reached
the output will shutdown for a time given by:
TC
SD
T
=•
210$
IMAX: This pin programs the maximum allowable
sourcing current. Since VDD is a regulated voltage, a
voltage divider can be derived from VDD to generate the
program level for IMAX. The current level at which the
output appears as a current source is equal to the
voltage on IMAX over the current sense resistor. If
desired, a controlled current start up can be programmed
with a capacitor on IMAX, and a programmed start delay
can be achieved by driving the shutdown with an open
collector/drain device into an RC network.
OUT: This pin provides gate output drive to the MOSFET
pass element.
PL: This feature ensures that the average MOSFET
power dissipation is controlled. A resistor is connected
from this pin to the drain of the NMOS pass element.
When the voltage across the NMOS exceeds 5V, current
will flow into the PL pin which adds to the fault timer
charge current, reducing the duty cycle from the 3%
level. When IPL>>36
µA, then the average MOSFET
power dissipation is given by:
P
avg IMAX
R
MOSFET
PL
=• •
110 $


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