CY7C131E, CY7C131AE

CY7C136E, CY7C136AE

Document Number: 001-64231 Rev. *E

Page 7 of 20

Busy/Interrupt Timing[17]

BUSY LOW from Address match

–

15–20

ns

BUSY HIGH from Address mismatch [18]

–

15–20

ns

BUSY LOW from CE LOW

–

15–20

ns

BUSY HIGH from CE HIGH [18]

–

15–20

ns

Port setup for priority

5

–5–

ns

BUSY HIGH to valid data

–

15–25

ns

Write data valid to read data valid [19]

–

25–30

ns

Write pulse to data delay [19]

–

30–45

ns

Interrupt Timing

R/W to INTERRUPT set time

–

15–25

ns

CE to INTERRUPT set time

–

15–25

ns

Address to INTERRUPT set time

–

15–25

ns

OE to INTERRUPT reset time [18]

–

15–25

ns

CE to INTERRUPT reset time [18]

–

15–25

ns

Address to INTERRUPT reset time [18]

–

15–25

ns

Switching Characteristics (continued)

Over the Operating Range

Description

7C131E-15/7C131AE-15

7C131E-25/7C136E-25

Unit

Min

Max

Min

Max

Notes

17. Test conditions used are Load 2.

18. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.

19. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes HIGH.

Port B’s address toggled.

CE for Port B is toggled.