CY7C131E, CY7C131AE

CY7C136E, CY7C136AE

Document Number: 001-64231 Rev. *E

Page 3 of 20

Pin Configurations

Figure 1. Pin Diagram - 52-pin PLCC (Top View)

Figure 2. Pin Diagram - 52-pin PQFP (Top View)

1

8

9

10

11

12

13

14

15

16

17

18

19

20

46

45

44

43

42

41

40

39

38

37

36

35

34

2122 23 24 25 26 27 28 29 30 31 32 33

7 6 5 4 3 2

52 51 50 49 48 47

NC

7C131E/7C131AE

7C136E/7C136AE

46

1

2

3

4

5

6

7

8

9

10

11

12

13

39

38

37

36

35

34

33

32

31

30

29

28

27

14

16 17 18 19 20 21 22 23 24 25 26

52 51

49 48 47

45 44 43 42 41 40

NC

7C131E/7C131AE

7C136E/7C131AE

[5]

[5]

[5]

[5]

50

15

Pin Definitions

Left Port

Right Port

Description

Chip Enable

Read/Write Enable

Output Enable

[5]

[5]

Address

Data Bus Input/Output

Interrupt Flag

Busy Flag

Power

GND

Ground

Selection Guide

Parameter

7C131E-15

7C131AE-15

7C131E-25

7C136E-25

7C131E-55

7C136E-55

7C136AE-55

Unit

Maximum Access Time

15

25

55

ns

Typical Operating Current

110

100

95

mA

50

45

45

mA

0.05

0.05

0.05

mA

Note

5. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.