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CY7C1339G-133AXC Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1339G-133AXC Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 22 page  CY7C1339G 4-Mbit (128 K × 32) Pipelined Sync SRAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05520 Rev. *N Revised June 25, 2013 4-Mbit (128 K × 32) Pipelined Sync SRAM Features ■ Registered inputs and outputs for pipelined operation ■ 128 K × 32 common I/O architecture ■ 3.3 V core power supply (VDD) ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 4.0 ns (for 133-MHz device) ■ Provide high-performance 3-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Available in Pb-free 100-pin TQFP package ■ “ZZ” sleep mode option Functional Description The CY7C1339G SRAM integrates 128 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:D], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1339G operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. A DDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BW E GW CE1 CE2 CE3 OE ENA BLE REGISTER OUTPUT REGISTERS SENSE AM PS OUTPUT BUFFERS E PIPELINED ENA BLE INPUT REGISTERS A 0, A 1, A BW B BW C BW D BW A MEMORY ARRA Y DQ s SLEEP CONTROL ZZ A [1:0] 2 DQA BY TE WRITE REGISTER DQB BY TE WRITE REGISTER DQC BY TE WRITE REGISTER DQD BY TE WRITE REGISTER DQA BY TE WRITE DRIVER DQB BY TE WRITE DRIVER DQC BY TE WRITE DRIVER DQD BY TE WRITE DRIVER Logic Block Diagram Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround. |
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