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CY7C136E-55JXC Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C136E-55JXC Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 20 page CY7C131E, CY7C131AE CY7C136E, CY7C136AE Document Number: 001-64231 Rev. *E Page 10 of 20 Switching Waveforms Figure 4. Read Cycle No. 1 [28, 29] Figure 5. Read Cycle No. 2 [28, 30] Figure 6. Write Cycle No. 1 (OE Three-States Data I/Os – Either Port) [31, 32] tRC tAA tOHA DATA VALID PREVIOUS DATAVALID DATA OUT ADDR Either Port ADDR Access tACE tLZOE tDOE tHZOE tHZCE DATA VALID DATA OUT CE OE tLZCE tPU ICC ISB tPD Either Port CE/OE Access tAW tWC DATA VALID HIGH IMPEDANCE tSCE tSA tPWE tHD tSD tHA CE R/W ADDR tHZOE OE DOUT DATAIN Either Port Notes 28. R/W is HIGH for read cycle. 29. Device is continuously selected, CE = VIL and OE = VIL. 30. Address valid prior to or coincident with CE transition LOW. 31. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. |
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