CY7C1425KV18

CY7C1412KV18

CY7C1414KV18

Document Number: 001-57825 Rev. *I

Page 11 of 33

Truth Table

The truth table for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [2, 3, 4, 5, 6, 7]

Operation

K

RPS WPS

DQ

DQ

Write cycle:

Load address on the rising edge of K;

input write data on K and K rising edges.

L–H

X

L

D(A + 0) at K(t)



D(A + 1) at K(t)



Read cycle:

Load address on the rising edge of K;

wait one and a half cycle; read data on C and C rising edges.

L–H

L

X

Q(A + 0) at C(t + 1)

 Q(A + 1) at C(t + 2) 

NOP: No operation

L–H

H

H

D = X

Q = high Z

D = X

Q = high Z

Standby: Clock stopped

Stopped

X

X

Previous state

Previous state

Write Cycle Descriptions

The write cycle description table for CY7C1412KV18 follow. [2, 8]

K

K

Comments

L

L

L–H

–

During the data portion of a write sequence



CY7C1412KV18

L

L

–

L–H During the data portion of a write sequence:

CY7C1412KV18

L

H

L–H

–

During the data portion of a write sequence:

CY7C1412KV18

L

H

–

L–H During the data portion of a write sequence



CY7C1412KV18

H

L

L–H

–

During the data portion of a write sequence



CY7C1412KV18

H

L

–

L–H During the data portion of a write sequence



CY7C1412KV18

H

H

L–H

–

No data is written into the devices during this portion of a write operation.

H

H

–

L–H No data is written into the devices during this portion of a write operation.

Notes

2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

3. Device powers up deselected with the outputs in a tristate condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

of a write cycle, as long as the setup and hold requirements are achieved.