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CY7C1481BV25 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1481BV25 Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 21 page  CY7C1481BV25 72-Mbit (2 M × 36) Flow-Through SRAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-74847 Rev. *A Revised May 24, 2013 72-Mbit (2 M × 36) Flow-Through SRAM Features ■ Supports 133 MHz bus operations ■ 2 M × 36 common I/O ■ 2.5 V core power supply (VDD) ■ 2.5 V I/O supply (VDDQ) ■ Fast clock to output time ❐ 6.5 ns (133 MHz version) ■ Provide high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed write ■ Asynchronous output enable ■ CY7C1481BV25 available in JEDEC standard Pb-free 100-pin TQFP package ■ IEEE 1149.1 JTAG compatible boundary scan ■ ZZ sleep mode option Functional Description The CY7C1481BV25 is a 2.5 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1481BV25 enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses are initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Selection Guide Description 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 305 mA Maximum CMOS Standby Current 120 mA |
Similar Part No. - CY7C1481BV25_13 |
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Similar Description - CY7C1481BV25_13 |
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