CY7C1472BV33-167AXI datasheet(11/34 Pages) CYPRESS

Part #	CY7C1472BV33-167AXI

Description	72-Mbit (2 M x 36/4 M 횞 18/1 M x 72) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 34 page

CY7C1470BV33

CY7C1472BV33

CY7C1474BV33

Document Number: 001-15031 Rev. *K

Page 11 of 34

Truth Table

The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. [1, 2, 3, 4, 5, 6, 7]

Operation

Address Used CE ZZ ADV/LD WE BWx OE CEN CLK

DQ

Deselect Cycle

None

H

L

X

L

L–H

Tri-State

Continue Deselect Cycle

None

X

L

H

X

L

L–H

Tri-State

Read Cycle (Begin Burst)

External

L

H

X

L

L–H Data Out (Q)

Read Cycle (Continue Burst)

L

H

X

L

L–H Data Out (Q)

NOP/Dummy Read (Begin Burst)

External

L

H

X

H

L

L–H

Tri-State

Dummy Read (Continue Burst)

L

H

X

H

L

L–H

Tri-State

Write Cycle (Begin Burst)

External

L

X

L

L–H

Data In (D)

Write Cycle (Continue Burst)

L

H

X

L

X

L

L–H

Data In (D)

NOP/Write Abort (Begin Burst)

None

L

H

X

L

L–H

Tri-State

Write Abort (Continue Burst)

L

H

X

H

X

L

L–H

Tri-State

Ignore Clock Edge (Stall)

Current

X

L

X

H

L–H

-

Sleep Mode

None

X

H

X

XXXX

X

Tri-State

Notes

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see Partial Write Cycle Description on page 12 for details.

2. Write is defined by WE and BW[a:d]. See Partial Write Cycle Description on page 12 for details.

3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQP[a:d] = tri-state when OE is

inactive or when the device is deselected, and DQs= data when OE is active.

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CY7C1472BV33-167AXI Datasheet(PDF) 11 Page - Cypress Semiconductor

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