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CY7C1481BV25-133AXI Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C1481BV25-133AXI Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 21 page CY7C1481BV25 Document Number: 001-74847 Rev. *A Page 10 of 21 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VDD Relative to GND .....–0.3 V to +3.6 V Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................–0.5 V to VDDQ + 0.5 V DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) ................................. >2001 V Latch Up Current ................................................... >200 mA Operating Range Range Ambient Temperature VDD VDDQ Commercial 0 °C to +70 °C 2.5 V – 5% / + 5% 2.5 V – 5% to VDD Industrial –40 °C to +85 °C Electrical Characteristics Over the Operating Range Parameter [8, 9] Description Test Conditions Min Max Unit VDD Power Supply Voltage 2.375 2.625 V VDDQ I/O Supply Voltage For 2.5 V I/O 2.375 VDD V VOH Output HIGH Voltage For 2.5 V I/O, IOH = –1.0 mA 2.0 – V VOL Output LOW Voltage For 2.5 V I/O, IOL = 1.0 mA – 0.4 V VIH Input HIGH Voltage [8] For 2.5 V I/O 1.7 VDD + 0.3 V V VIL Input LOW Voltage [8] For 2.5 V I/O –0.3 0.7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ –5 5 A Input Current of MODE Input = VSS –30 – A Input = VDD –5 A Input Current of ZZ Input = VSS –5 – A Input = VDD –30 A IOZ Output Leakage Current GND VI VDDQ, Output Disabled –5 5 A IDD [10] VDD Operating Supply Current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 7.5 ns cycle, 133 MHz –305 mA ISB1 Automatic CE Power Down Current – TTL Inputs Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching 7.5 ns cycle, 133 MHz –170 mA ISB2 Automatic CE Power Down Current – CMOS Inputs Max. VDD, Device Deselected, VIN VDD – 0.3 V or VIN 0.3 V, f = 0, inputs static 7.5 ns cycle, 133 MHz –120 mA ISB3 Automatic CE Power Down Current – CMOS Inputs Max. VDD, Device Deselected, VINVDDQ – 0.3 V or VIN 0.3 V, f = fMAX, inputs switching 7.5 ns cycle, 133 MHz –170 mA ISB4 Automatic CE Power Down Current – TTL Inputs Max. VDD, Device Deselected, VIN VDD – 0.3 V or VIN 0.3 V, f = 0, inputs static 7.5 ns cycle, 133 MHz –135 mA Notes 8. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 9. TPower-up: assumes a linear ramp from 0 V to VDD(minimum) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 10. The operation current is calculated with 50% read cycle and 50% write cycle. |
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