CY7C1643KV18-400BZXC datasheet(1/31 Pages) CYPRESS

Part #	CY7C1643KV18-400BZXC

Description	144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C1643KV18, CY7C1645KV18

144-Mbit QDR® II+ SRAM Four-Word Burst

Architecture (2.0 Cycle Read Latency)

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document Number: 001-44059 Rev. *I

Revised February 22, 2013

144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 450-MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 900 MHz) at 450 MHz

■ Available in 2.0-clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Quad data rate (QDR®) II+ operates with 2.0-cycle read latency

when DOFF is asserted high

■ Operates similar to QDR I device with one cycle read latency

when DOFF is asserted low

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD

[1]

❐ Supports both 1.5-V and 1.8-V I/O supply

■ High-speed transceiver logic (HSTL) Inputs and variable drive

HSTL output buffers

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(15 × 17 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1643KV18 – 8 M × 18

CY7C1645KV18 – 4 M × 36

Functional Description

The

CY7C1643KV18,

and

CY7C1645KV18

are

1.8-V

synchronous pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turnaround” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ read and write ports are completely

independent of one another. To maximize data throughput, both

read and write ports are equipped with DDR interfaces. Each

address location is associated with four 18-bit words

(CY7C1643KV18), or 36-bit words (CY7C1645KV18) that burst

sequentially into or out of the device. Because data is transferred

into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turnarounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description

450 MHz

400 MHz

Unit

Maximum operating frequency

450

400

MHz

Maximum operating current

× 18

940

860

mA

× 36

1290

1170

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.

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